- Oct 27, 2021
- Oct 11, 2021
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enjoy-digital authored
Add support for QMTech 10CL006 board
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enjoy-digital authored
rz_easyfpga: cleanup and ease of use
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Florent Kermarrec authored
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- Oct 07, 2021
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Florent Kermarrec authored
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- Oct 05, 2021
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Hans Baier authored
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- Oct 03, 2021
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alainlou authored
- update README - delete some unnecessary toolchain commands (copied from trenz boards) - use minimal cpu_variant by default when vexriscv is selected
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- Oct 01, 2021
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Florent Kermarrec authored
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Florent Kermarrec authored
Untested.
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- Sep 30, 2021
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
Compiles but untested on hardware.
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Florent Kermarrec authored
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- Sep 29, 2021
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Florent Kermarrec authored
Allows building bare metal demo and running it directly on these boards.
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- Sep 28, 2021
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enjoy-digital authored
Wukong board improvements
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- Sep 27, 2021
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Florent Kermarrec authored
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- Sep 24, 2021
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Benjamin Herrenschmidt authored
This adds support for v2 of the board via a --board-version argument and a way to select the FPGA speed grade via a --speed-grade argument. Note that the speed grade now defaults to -1. QMTech confirmed that V1 of the board were made in two batches, one with -1 and one with -2, while V2 of the board is all -1. So -1 is the safer default. This also fixes the inversion of j10 and j11 and a typo in the pin definition of jp3 Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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- Sep 23, 2021
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enjoy-digital authored
Initial Digilent Atlys support
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Florent Kermarrec authored
Build tested with ./digilent_atlys.py --with-ethernet --build.
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enjoy-digital authored
rz_easyfpga: adjust SDRAM clk phase, also add 1:2 rate
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- Sep 22, 2021
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alainlou authored
- also add 1:2 rate
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- Sep 21, 2021
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Alain Lou authored
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- Sep 20, 2021
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Florent Kermarrec authored
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Florent Kermarrec authored
With colorbars for now, need to free up BRAMS for Video Terminal (or finish HyperRAM support).
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Florent Kermarrec authored
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Florent Kermarrec authored
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- Sep 17, 2021
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Florent Kermarrec authored
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Florent Kermarrec authored
sipeed_tang_nano: Add SPI Flash, Enable CPU and use new external SPI Flash support from OpenFPGALoader. ./sipeed_tang_nano_4k.py --cpu-type=vexriscv --cpu-variant=lite --build --flash __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Build your hardware, easily! (c) Copyright 2012-2021 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on Sep 17 2021 15:54:08 BIOS CRC passed (6cc6de6d) Migen git sha1: a5bc262 LiteX git sha1: 46cd9c5a --=============== SoC ==================-- CPU: VexRiscv_Lite @ 27MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 64KiB SRAM: 8KiB FLASH: 4096KiB --========== Initialization ============-- Initializing W25Q32 SPI Flash @0x80000000... SPI Flash clk configured to 13 MHz Memspeed at 0x80000000 (Sequential, 4.0KiB)... Read speed: 1.3MiB/s Memspeed at 0x80000000 (Random, 4.0KiB)... Read speed: 521.9KiB/s --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro Timeout No boot medium found --============= Console ================-- litex>
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- Sep 16, 2021
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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