Unverified Commit 610e82d7 authored by Alain Lou's avatar Alain Lou Committed by GitHub
Browse files

Add initial RZ-EasyFPGA support! (#270)

parent d5eea942
......@@ -151,6 +151,7 @@ The Colorlight5A is a very nice board to start with, cheap, powerful, easy to us
| Nexys4DDR | Xilinx Artix7 | XC7A100T | 100MHz | FTDI | 16-bit 128MB DDR2 | No | 100Mbps RMII | 16MB QSPI* | Yes |
| Nexys Video | Xilinx Artix7 | XC7A200T | 100MHz | FTDI | 16-bit 512MB DDR3 | No | 1Gbps RMII | 32MB QSPI* | Yes |
| QMTech XC7A35T | Xilinx Artix7 | XC7A35T | 100MHz | FTDI | 16-bit 256MB DDR3 | No | 1Gbps GMII** | 16MB QSPI | Yes**|
| RZ-EasyFPGA | Intel Cyclone4 | EP4CE6 | 25MHz | IOs | 16-bit 8MB SDR | No | No | No | No |
| SP605 | Xilinx Spartan6 | XC6SLX45T | 100MHz | FTDI | 16-bit 128MB DDR3* | Gen1 X1* | 1Gbps GMII | 8MB QSPI* | Yes* |
| Tagus | Xilinx Artix7 | XC7A200T | 100MHz | PCIe | 16-bit 256MB DDR3 | Gen2 X1 | 1Gbps-BASE-X* | 16MB QSPI* | No |
| VC707 | Xilinx Virex7 | XC7VX485T | 125MHz | FTDI | 64-bit 1GB DDR3 | Gen3 X8* | 1Gbps GMII | 16MB QSPI* | Yes* |
......
......@@ -25,6 +25,7 @@ vendors = [
"qwertyembedded",
"radiona",
"rhsresearchllc",
"rz",
"saanlima",
"scarabhardware",
"siglent",
......
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 Alain Lou <alainzlou@gmail.com>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk
("clk50", 0, Pins("23"), IOStandard("3.3-V LVTTL")),
# Leds
("user_led", 0, Pins("84"), IOStandard("3.3-V LVTTL")),
("user_led", 1, Pins("85"), IOStandard("3.3-V LVTTL")),
("user_led", 2, Pins("86"), IOStandard("3.3-V LVTTL")),
("user_led", 3, Pins("87"), IOStandard("3.3-V LVTTL")),
# Serial
("serial", 0,
# Uses the 9 pin serial connector
Subsignal("tx", Pins("114"), IOStandard("3.3-V LVTTL")),
Subsignal("rx", Pins("115"), IOStandard("3.3-V LVTTL"))
),
# SDRAM
# It may help to add a header cable to some pins to mitigate suspected electrical problems on the board
# (especially pin 67, but adding cables to the whole addr bus seemed to be the most robust)
("sdram_clock", 0, Pins("43"), IOStandard("3.3-V LVTTL")),
("sdram", 0,
Subsignal("a", Pins(
"76 77 80 83 68 67 66 65",
"64 60 75 59")),
Subsignal("ba", Pins("73 74")),
Subsignal("cs_n", Pins("72")),
Subsignal("cke", Pins("58")),
Subsignal("ras_n", Pins("71")),
Subsignal("cas_n", Pins("70")),
Subsignal("we_n", Pins("69")),
Subsignal("dq", Pins(
"28 30 31 32 33 34 38 39",
"54 53 52 51 50 49 46 44")),
Subsignal("dm", Pins("42 55")),
IOStandard("3.3-V LVTTL")
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(AlteraPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
def __init__(self):
AlteraPlatform.__init__(self, "EP4CE6E22C8", _io)
def create_programmer(self):
return USBBlaster()
def do_finalize(self, fragment):
AlteraPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
# Generate PLL clock in STA
self.toolchain.additional_sdc_commands.append("derive_pll_clocks")
# Calculates clock uncertainties
self.toolchain.additional_sdc_commands.append("derive_clock_uncertainty")
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
# Copyright (c) 2021 Alain Lou <alainzlou@gmail.com>
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse
from migen import *
from litex.build.io import DDROutput
from litex_boards.platforms import easyfpga
from litex.soc.cores.clock import CycloneIVPLL
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
from litedram.modules import MT48LC4M16
from litedram.phy import GENSDRPHY
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
# # #
# Clk / Rst
clk50 = platform.request("clk50")
# PLL
self.submodules.pll = pll = CycloneIVPLL(speedgrade="-8")
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(clk50, 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
# SDRAM clock
self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(25e6), with_led_chaser=True, **kwargs):
platform = easyfpga.Platform()
# Limit internal rom and sram size
kwargs["integrated_rom_size"] = 0x6200
kwargs["integrated_sram_size"] = 0x1000
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on RZ-EasyFPGA",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram",
phy = self.sdrphy,
module = MT48LC4M16(sys_clk_freq, "1:1"), # Hynix HY57V641620FTP-7
l2_cache_size = 0
)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on RZ-EasyFPGA")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq", default=25e6, help="System clock frequency (default: 25MHz)")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".sof"))
if __name__ == "__main__":
main()
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