Commit 4a34179f authored by minute's avatar minute
Browse files

mnt_rkx7: add litescope and some debugging

parent 922f6daf
......@@ -28,6 +28,12 @@ _io = [
IOStandard("LVCMOS33")
),
("litescope_serial", 0,
Subsignal("tx", Pins("C17")),
Subsignal("rx", Pins("C16")),
IOStandard("LVCMOS33")
),
# SPIFlash
("spiflash4x", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("C23")),
......
......@@ -117,6 +117,12 @@ class BaseSoC(SoCCore):
self.submodules.i2c1 = I2CMaster(platform.request("i2c", 1))
self.submodules.i2c2 = I2CMaster(platform.request("i2c", 2))
# JTAG
#self.add_jtagbone()
# LiteScope UART
self.add_uartbone(name="litescope_serial")
# MIPI DSI ---------------------------------------------------------------------------------
dsi = platform.request("dsi")
self.comb += dsi.refclk.eq(self.crg.cd_dsiref.clk)
......@@ -144,7 +150,10 @@ class BaseSoC(SoCCore):
self.comb += usb_pipe_ctrl.phy_reset_n.eq(usb2_phy_reset_n)
self.comb += usb_pipe_ctrl.power_down.eq(usb2_powerdown)
self.comb += usb_enable.eq(usb2_enable)
#self.comb += usb_pipe_ctrl.tx_elecidle.eq(Signal(reset=0))
self.comb += usb_pipe_ctrl.tx_elecidle.eq(Signal(reset=0))
self.comb += usb_pipe_ctrl.tx_detrx_lpbk.eq(Signal(reset=0))
usb_pipe_status = platform.request("usb_pipe_status")
# External verilog sources of ultraembedded's USB Host and ULPI/UTMI wrapper
platform.add_verilog_include_path(os.path.join("core_usb_host", "src_v"))
......@@ -232,6 +241,9 @@ class BaseSoC(SoCCore):
# Wire for USB host interrupt line
usb_host_intr = Signal()
usbh_dbg_state = Signal(4)
usbh_dbg_token = Signal(16)
usb_host = Instance(
"usbh_host",
......@@ -239,6 +251,9 @@ class BaseSoC(SoCCore):
i_rst_i = Signal(reset=0),
o_intr_o = usb_host_intr,
o_dbg_state_o = usbh_dbg_state,
o_dbg_token_o = usbh_dbg_token,
# UTMI
i_utmi_data_in_i = utmi.data_in,
i_utmi_txready_i = utmi.txready,
......@@ -279,6 +294,32 @@ class BaseSoC(SoCCore):
# Connection of USB Host interrupt to CPU (yet unused)
self.comb += self.cpu.interrupt[16].eq(usb_host_intr)
# LiteScope
analyzer_signals = [
ulpi_data.din,
#ulpi_data.dout,
utmi.linestate,
utmi.data_out,
utmi.txvalid,
utmi.rxerror,
utmi.rxvalid,
usb_ulpi.dir,
usb_ulpi.stp,
usb_ulpi.nxt,
usbh_dbg_state,
usb_pipe_status.pwr_present,
usb_pipe_status.phy_status,
usb_pipe_status.rx_status,
usb_pipe_status.rx_elecidle,
]
from litescope import LiteScopeAnalyzer
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
depth = 512,
clock_domain = "ulpi",
csr_csv = "analyzer.csv")
# Build --------------------------------------------------------------------------------------------
def main():
......@@ -308,6 +349,9 @@ def main():
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
args.csr_csv="csr.csv"
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
......
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