- Aug 07, 2018
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Troy Kisky authored
Includes hsolo1g and hquad2g h.h: CONFIG_IPUV3_CLK 264000000 h: setup_dispay is done in fbpanel h: add CONFIG_CMD_GPIO h: explicit fbp_detect_i2c h: verify port in board_ehci_hcd_init h: use boundary.h h: setup rgb_gpio_pads in board_early_init_f h: add CONFIG_SPI_FLASH_SPANSION h: hquad2g_defconfig add CONFIG_BLOCK_CACHE hsolo1g: hsolo1g_defconfig add CONFIG_BLOCK_CACHE h: use common code for eth init h: eth.c now in common directory h: move misc_init_r/do_kbd to common h: move mmc_init/ dram_init/ overwrite_console/ common_board_init/ splash_screen_prepare/ board_cfb_skip to common h: use common 1066mhz_4x256mx16.cfg h: add CONFIG_SPI_FLASH_GIGADEVICE: to defconfigs h: use common ddr scripts h: port to v2018.07 Signed-off-by:
Troy Kisky <troy.kisky@boundarydevices.com> h: update to v2017.01 h: update to v2017.03 Signed-off-by:
Gary Bisson <gary.bisson@boundarydevices.com>
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Troy Kisky authored
eo: add eo_duallite_defconfig eo.h: CONFIG_IPUV3_CLK 264000000 eo: use nitrogen6x/ddr-setup.cfg eo: use MX6Q or MX6DL instead of MX6QDL eo: add CONFIG_CMD_GPIO eo: explicit fbp_detect_i2c eo: add wlmac eo: use boundary.h eo: add CONFIG_SPI_FLASH_SPANSION eo: eo_defconfig add CONFIG_BLOCK_CACHE eo_duallite: eo_duallite_defconfig add CONFIG_BLOCK_CACHE eo: use common code for eth init eo: eth.c now in common directory eo: move misc_init_r/do_kbd to common eo: move mmc_init/ dram_init/ overwrite_console/ common_board_init/ splash_screen_prepare/ board_cfb_skip to common eo: use common 1066mhz_4x128mx16.cfg eo: add CONFIG_SPI_FLASH_GIGADEVICE: to defconfigs eo: use common ddr scripts eo: port to v2018.07 Signed-off-by:
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Troy Kisky authored
dash.h: CONFIG_IPUV3_CLK 264000000 dash: add CONFIG_CMD_GPIO dash: explicit fbp_detect_i2c dash: verify port in board_ehci_hcd_init dash: use boundary.h dash: add CONFIG_SPI_FLASH_SPANSION dash: dash_defconfig add CONFIG_BLOCK_CACHE dash: use common code for eth init dash: eth.c now in common directory dash: move misc_init_r/do_kbd to common dash: move mmc_init/ dram_init/ overwrite_console/ common_board_init/ splash_screen_prepare/ board_cfb_skip to common dash: add CONFIG_SPI_FLASH_GIGADEVICE: to defconfigs dash: add dash_q1g.cfg dash: port to v2018.07 Signed-off-by:
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Troy Kisky authored
cob2: 9 board sample for q1g ddr calibration cob2: add CONFIG_SPI_FLASH_GIGADEVICE: to defconfigs cob2: use common ddr script cob2: port to v2018.07 Signed-off-by: -
Troy Kisky authored
cob.h: CONFIG_IPUV3_CLK 264000000 cob: use nitrogen6x/ddr-setup.cfg cob: add CONFIG_CMD_GPIO cob: explicit fbp_detect_i2c cob: verify port in board_ehci_hcd_init cob: use boundary.h cob: setup rgb_gpio_pads in board_early_init_f cob: add CONFIG_SPI_FLASH_SPANSION cob.h: skip fuses, they do it themselves cob: cob_defconfig add CONFIG_BLOCK_CACHE cob: use common code for eth init cob: eth.c now in common directory cob: move misc_init_r/do_kbd to common cob: move mmc_init/ dram_init/ overwrite_console/ common_board_init/ splash_screen_prepare/ board_cfb_skip to common cob: use common 1066mhz_4x128mx16.cfg cob: add CONFIG_SPI_FLASH_GIGADEVICE: to defconfigs cob: use common ddr script cob: port to v2018.07 Signed-off-by:
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Gary Bisson authored
cnt: add defconfig for 1GB of RAM version cnt: fix boot devs configuration cnt: update to v2017.01 cnt: update to v2017.03 cnt.h: add custom BOOT_TARGET_DEVICES priority Signed-off-by:
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Troy Kisky authored
cid_tab: delay 3P7V rail turn on cid_tab: turn off boost before poweroff cid_tab: add CONFIG_SPI_FLASH_GIGADEVICE: to defconfigs cid_tab: tamper support checking TAMPER pin cid_tab: use common ddr script cid_tab: port to v2018.07 Signed-off-by:
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Gary Bisson authored
cid_2g_defconfig: reduce bootdelay to 0 cid: limit boot sequence to eMMC cid: start fastboot when power and reset are pressed Signed-off-by:
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Troy Kisky authored
cad.h: CONFIG_IPUV3_CLK 264000000 cad: add CONFIG_CMD_GPIO cad: explicit fbp_detect_i2c cad: use VDF_SPI_QVGA cad: use boundary.h cad: setup rgb_gpio_pads in board_early_init_f cad: add CONFIG_SPI_FLASH_SPANSION cad: cad_defconfig add CONFIG_BLOCK_CACHE cad: use common code for eth init cad: eth.c now in common directory cad: move misc_init_r/do_kbd to common cad: move mmc_init/ dram_init/ overwrite_console/ common_board_init/ splash_screen_prepare/ board_cfb_skip to common cad: add CONFIG_SPI_FLASH_GIGADEVICE: to defconfigs cad: use common ddr script cad: port to v2018.07 Signed-off-by:
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Troy Kisky authored
bt2: GPS is thru i2c now bt2: swap J6/J7 bt2: rename J6/J7 - J5V/J12v bt2: use nitrogen6x clock.cfg/ddr-setup.cfg bt2: 1066mhz_4x512mx16.cfg, remove confusing comment bt2: add/use 1066mhz_4x512mx16-r0.cfg for 4G memory option bt2: add CONFIG_CMD_GPIO bt2: explicit fbp_detect_i2c bt2: add wlmac bt2: increase refresh rate for 4G-rank0 bt2: setup rgb_gpio_pads in board_early_init_f bt2: add CONFIG_SPI_FLASH_SPANSION bt2: bt2_2g_defconfig add CONFIG_BLOCK_CACHE bt2_4g: bt2_4g_defconfig add CONFIG_BLOCK_CACHE bt2: use common code for eth init bt2: eth.c now in common directory bt2: move mmc_init/ dram_init/ overwrite_console/ common_board_init/ splash_screen_prepare/ board_cfb_skip to common bt2: use common 1066mhz_4x256mx16.cfg bt2: add CONFIG_SPI_FLASH_GIGADEVICE: to defconfigs bt2: use common ddr scripts bt2: port to v2018.07 Signed-off-by:
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Troy Kisky authored
Two configurations bt2g and bt4g for two different memory layouts bt.h: CONFIG_IPUV3_CLK 264000000 bt: rename J6/J7 to J12V/J5V bt: use nitrogen6x clock.cfg/ddr-setup.cfg bt: add CONFIG_CMD_GPIO bt: explicit fbp_detect_i2c bt: use boundary.h bt: add CONFIG_SPI_FLASH_SPANSION bt.h: use BD_CMA to specify cma= on cmd_line bt: bt2g_defconfig add CONFIG_BLOCK_CACHE bt4g: bt4g_defconfig add CONFIG_BLOCK_CACHE bt: use common code for eth init bt: eth.c now in common directory bt: move misc_init_r/do_kbd to common bt: move mmc_init/ dram_init/ overwrite_console/ common_board_init/ splash_screen_prepare/ board_cfb_skip to common bt: use common 1066mhz_4x256mx16.cfg bt: add CONFIG_SPI_FLASH_GIGADEVICE: to defconfigs bt: use common ddr scripts bt: port to v2018.07 Signed-off-by:
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Troy Kisky authored
ash2: KEY_COL0 must be UART4_TX_DATA ash2: add power_init_board because mdelay cannot be used in board_early_init_f ash2: use common 800mhz_4x128mx16.cfg, and calibrate ddr ash2: rgb24 vs rgb66 panel have different backlight active levels ash2: fixup dtb backlight levels ash2: add CONFIG_SPI_FLASH_GIGADEVICE: to defconfigs ash2: use common ddr script ash2: port to v2018.07 Signed-off-by: -
Troy Kisky authored
ash: add poweroff command ash: fix some input gpios(CH_ON_RBL/SG_ON_RBL/DOOR_CLOSED ash: use nitrogen6x/clock.cfg ash: use nitrogen6x ddr-setup.cfg ash: remove micrel phy references(only atheros on this board) ash: add CONFIG_CMD_GPIO ash: set rgb_gpio_pads ash: TP86 becomes lvds backlight enable ash: explicit fbp_detect_i2c ash: default uart1 to rs232 ash: use 800mhz for memory ash: use boundary.h ash: GP_BSL_CB_ON_OFF high, TX23D200_18 default dispay ash: add CONFIG_VIDEO_SKIP_VERSION ash: GP_BSL_CB_ON_OFF default to low again ash: add EIM_EB2 for sd card power control ash: add CONFIG_SPI_FLASH_SPANSION ash: ash_defconfig add CONFIG_BLOCK_CACHE ash: use common code for eth init ash: eth.c now in common directory ash: move misc_init_r/do_kbd to common ash: move mmc_init/ dram_init/ overwrite_console/ common_board_init/ splash_screen_prepare/ board_cfb_skip to common ash: gpio3 is power off, don't redefine ash: add power_init_board because mdelay cannot be used in board_early_init_f ash: use common 800mhz_4x128mx16.cfg ash: rgb24 vs rgb66 panel have different backlight active levels ash: fixup dtb backlight levels ash: add CONFIG_SPI_FLASH_GIGADEVICE: to defconfigs ash: use common ddr script ash: port to v2018.07 Signed-off-by:
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Troy Kisky authored
ap: forgot file include/configs/ap.h ap: ap_q2g_defconfig: add CONFIG_SPI_FLASH_GIGADEVICE ap: add bootscript_lp8860_eprom.txt ap: add verification to bootscript_lp8860_eprom.txt ap: use common ddr script ap: port to v2018.07 Signed-off-by: -
Gary Bisson authored
acl: update to v2017.01 acl update to v2017.03 acl: fix scanner gpios initialization Signed-off-by:
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Gary Bisson authored
ys: update to v2017.01 ys: update to v2017.03 Signed-off-by:
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Troy Kisky authored
a: add usb hub reset/uart3/uart4/flexcan pins a: keep USB Huawei Modem in reset a: add leds rx active/tx active a: remove printf of board_mmc_init a.h: add cmd_custom to avoid update u-boot warning a: add CONFIG_CMD_GPIO a: remove redundant CONFIG_CMD_GPIO a: verify port in board_ehci_hcd_init a: use boundary.h a: call preboot_keys a: add CONFIG_SPI_FLASH_SPANSION a: add RV4162 rtc on I2C2 a: a_defconfig add CONFIG_BLOCK_CACHE a: use common code for eth init a: eth.c now in common directory a: move misc_init_r/do_kbd to common a: move mmc_init/ dram_init/ overwrite_console/ common_board_init/ splash_screen_prepare/ board_cfb_skip to common a: add CONFIG_SPI_FLASH_GIGADEVICE: to defconfigs a: add a_s512m.cfg a: port to v2018.07 Signed-off-by:
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- Jul 27, 2018
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Ye.Li authored
To resolve USB camera bandwidth issue, the patch sets recommended AQoS setting from IC team value for peripheral and only on imx6qp. The address is: 0xbb0608, the value is: 0x80000201 Signed-off-by:Ye.Li <B37916@freescale.com> (cherry picked from commit d00e9400bfbfb097ab5b0b26fae92db3dc1dd047)
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- Jun 19, 2018
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Michal Simek authored
cpu_cmd() is reading cpu number via simple_strtoul() which is always unsigned type. Platform code implementations are not expecting that nr can be negative and there is not checking in the code for that too. This patch is using u32 type for cpu number to make sure that platform code get proper value range. Signed-off-by:Michal Simek <michal.simek@xilinx.com>
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- May 18, 2018
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Jagan Teki authored
MX6DL Mamoj boards has Freescale PFUZE100 PMIC, add support for it through DM_PMIC dt definition. pmic log: Reviewed-by:
Stefano Babic <sbabic@denx.de> ======== => pmic list | Name | Parent name | Parent uclass @ seq | pfuze100@08 | i2c@021f8000 | i2c @ 3 => pmic dev pfuze100@08 dev: 0 @ pfuze100@08 => pmic dump Dump pmic: pfuze100@08 registers 0x00: 10 00 00 21 00 01 3f 01 00 7f 00 00 00 00 00 81 0x10: 00 00 3f 00 00 00 00 00 00 00 00 10 00 00 00 00 0x20: 2b 2b 2b 08 c4 00 00 00 00 00 00 00 00 00 2b 2b 0x30: 2b 08 c4 00 00 72 72 72 08 d4 00 00 2c 2c 2c 08 0x40: e4 00 00 2c 2c 2c 08 e4 00 00 6f 6f 6f 08 f4 00 0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0x60: 00 00 00 00 00 00 48 00 00 00 10 06 1e 1e 17 10 0x70: 1a 1f 00 00 00 00 00 00 00 00 00 00 00 00 00 Signed-off-by:
Jagan Teki <jagan@amarulasolutions.com> Signed-off-by:
Simone CIANNI <simone.cianni@bticino.it> Signed-off-by:
Raffaele RECALCATI <raffaele.recalcati@bticino.it>
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Jagan Teki authored
i.MX6DL Mamoj has i2c3 and i2c4 buses, add support through DM_I2C with dt definition. i2c log: Reviewed-by:
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Jagan Teki authored
Add initial support for i.MX6DL BTicino Mamoj board. Mamoh board added: - SPL - SPL_DM - SPL_OF_CONTROL - DM for U-Boot proper - OF_CONTROL for U-Boot proper - eMMC - FEC - Boot from eMMC - Boot from USB SDP Signed-off-by:
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- May 17, 2018
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Peter Robinson authored
It makes sense to select the MP multi processor option at the same time we select the other SMP options needed for SMP capable i.MX6 SoCs. Signed-off-by:Peter Robinson <pbrobinson@gmail.com>
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Ian Ray authored
This replaces TARGET_GE_B{4,6,8}50V3 with common TARGET_GE_BX50V3. The boards are identified automatically at runtime. Signed-off-by:Ian Ray <ian.ray@ge.com> Signed-off-by:
Nandor Han <nandor.han@ge.com> Signed-off-by:
Sebastian Reichel <sebastian.reichel@collabora.co.uk>
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- May 07, 2018
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Tom Rini authored
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by:Tom Rini <trini@konsulko.com>
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- Apr 26, 2018
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Sébastien Szymanski authored
When booting in Serial Downloader mode load the U-Boot image using ymodem. Signed-off-by:Sébastien Szymanski <sebastien.szymanski@armadeus.com>
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Sébastien Szymanski authored
Since commit commit 152038ea ("i.MX6UL: icore: Add SPL_OF_CONTROL support") the OPOS6UL board doesn't boot anymore. Adding SPL_DM support makes the board boot again. Fixes: commit 152038ea ("i.MX6UL: icore: Add SPL_OF_CONTROL support") Signed-off-by:
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- Apr 15, 2018
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Lukasz Majewski authored
This commit provides support for Kieback & Peter GmbH IMX6Q based TPC board. U-boot console output: U-Boot SPL 2018.05-rc1-00005-g631e2d01fd (Apr 04 2018 - 21:16:24 +0200) Trying to boot from MMC1 U-Boot 2018.05-rc1-00005-g631e2d01fd (Apr 04 2018 - 21:16:24 +0200) CPU: Freescale i.MX6Q rev1.5 996 MHz (running at 792 MHz) CPU: Extended Commercial temperature grade (-20C to 105C) at 37C Reset cause: POR Board: K+P KP_IMX6Q_TPC i.MX6Q Watchdog enabled I2C: ready DRAM: 2 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... OK In: serial Out: serial Err: serial Net: FEC [PRIME] Autoboot in 3 seconds -
Marek Vasut authored
When the DDR calibration is enabled, a situation may happen that it will fail on a few select boards out of a whole production lot. In particular, after the first write leveling stage, the MPWLDECTRLx registers will contain a value 0x1nn , for nn usually being 0x7f or slightly lower. What this means is that the HW write leveling detected that the DQS rising edge on one or more bundles arrives slightly _after_ CLK and therefore when the DDR DRAM samples CLK on the DQS rising edge, the CLK signal is already high (cfr. AN4467 rev2 Figure 7 on page 18). The HW write leveling then ends up adding almost an entire cycle (thus the 0x17f) to the DQS delay, which indeed aligns it, but also triggers subsequent calibration failure in DQS gating due to this massive offset. There are two observations here: - If the MPWLDECTRLx value is corrected from 0x17f to 0x0 , then the DQS gating passes, the entire calibration passes as well and the DRAM is perfectly stable even under massive load. - When using the NXP DRAM calibrator for iMX6/7, the value 0x17f or so in MPWLDECTRx register is not there, but it is replaced by 0x0 as one would expect. Someone from NXP finally explains why, quoting [1]: " Having said all that, the DDR Stress Test does something that we do not advertise to the users. The Stress Test iself looks at the values of the MPWLDECTRL0/1 fields before reporting results, and if it sees any filed with a value greater than 200/256 delay (reported as half-cycle = 0x1 and ABS_OFFSET > 0x48), the DDR Stress test will reset the Write Leveling delay for this lane to 0x000 and not report it in the log. The reason that the DDR Stress test does this is because a delay of more than 78% a clock cycle means that the DQS edge is arriving within the JEDEC tolerence of 25% of the clock edge. In most cases, DQS is arriving < 5% tCK of the SDCLK edge in the early case, and it does not make sense to delay the DQS strobe almost a full clock cycle and add extra latency to each Write burst just to make the two edges align exactly. In this case, we are guilty of making a decision for the customer without telling them we are doing it so that we don't have to provide the above explanation to every customer. They don't need to know it. " This patch adds the correction described above, that is if the MPWLDECTRx value is over 0x148, the value is corrected back to 0x0. [1] https://community.nxp.com/thread/456246 Signed-off-by:Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by:
Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by:
Eric Nelson <eric@nelint.com> Reviewed-by:
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- Mar 05, 2018
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Masahiro Yamada authored
Thomas reported U-Boot failed to build host tools if libfdt-devel package is installed because tools include libfdt headers from /usr/include/ instead of using internal ones. This commit moves the header code: include/libfdt.h -> include/linux/libfdt.h include/libfdt_env.h -> include/linux/libfdt_env.h and replaces include directives: #include <libfdt.h> -> #include <linux/libfdt.h> #include <libfdt_env.h> -> #include <linux/libfdt_env.h> Reported-by:
Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com>
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- Feb 22, 2018
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Jagan Teki authored
Currently SPL_LOAD_FIT is unable to boot from nand on i.MX6QDL platform, so enable only for MMC boards. Signed-off-by:
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- Feb 04, 2018
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Peng Fan authored
Move i.MX6/7 bootaux code to imx_bootaux.c. The i.MX6/7 has different src layout, so define M4 reg offset to ease the cleanup. Redefine the M4 related BIT for share common code. Signed-off-by:Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com>
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Peng Fan authored
Move imx_get_mac_from_fuse to a new mac.c for i.MX6/7. Since fuse regs structure are different for i.MX6/7, use mac address offset in code and define a new local struture imx_mac_fuse. Also sort the config order. Signed-off-by:
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- Jan 24, 2018
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Álvaro Fernández Rojas authored
wait_for_bit callers use the 32 bit LE version Signed-off-by:
Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by:
Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by:
Jagan Teki <jagan@openedev.com>
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- Jan 12, 2018
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Christopher Spinrath authored
Like many other i.MX6 based boards, there are multiple variants of the cm-fx6 module featuring different SoC variants. Furthermore, the module can be paired with multiple baseboards. At the same time modern distribution like Fedora require U-Boot to select a proper devicetree which depends on the SoC variant and the baseboard. Thus, export the SoC variant and the actual board to the environment following the conventions of other i.MX6 devices (e.g. the NXP boards) such that the environment can select a devicetree file to load. For now, we only know for sure that the cm-fx6 module and the SB-fx6m baseboard amount to a Utilite Computer variant (depending on the SoC). Further combinations may be added in the future; e.g. CompuLab's evaluation board once someone can verify the identification string stored in its eeprom. Signed-off-by:
Christopher Spinrath <christopher.spinrath@rwth-aachen.de> Reviewed-by:
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Fabio Estevam authored
i.MX6ULL also does not have a MMDC_P1_BASE_ADDR, so do not try to access it. Signed-off-by:
Stefano Babic <ssbabic@denx.de>
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Stefano Babic authored
Board has 1GB RAM and boots from SD Card U-Boot SPL 2018.01-rc3-00005-ga1898b8 (Jan 02 2018 - 13:48:54) BT_FUSE_SEL already fused, will do nothing Trying to boot from MMC1 U-Boot 2018.01-rc3-00005-ga1898b8 (Jan 02 2018 - 13:48:54 +0100) CPU: Freescale i.MX6DL rev1.2 996 MHz (running at 792 MHz) CPU: Commercial temperature grade (0C to 95C) at 40C Reset cause: POR I2C: ready DRAM: 1 GiB MMC: FSL_SDHC: 0 In: serial Out: serial Err: serial Net: FEC [PRIME] Signed-off-by:
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- Jan 08, 2018
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Stefan Agner authored
The i.MX 6UL/ULL feature a Cortex-A7 CPU which suppor the ARM generic timer. This change makes use of the ARM generic timer in U-Boot. This is crucial to make the ARM generic timers usable in Linux since timer_init() initalizes the system counter module, which is necessary to use the generic timers CP15 registers. Signed-off-by:
Stefan Agner <stefan.agner@toradex.com> Reviewed-by:
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Stefan Agner authored
Introduce a new config symbol to select the i.MX General Purpose Timer (GPT). Signed-off-by:
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- Jan 04, 2018
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Fabio Estevam authored
Since commit 051ba9e0 ("Kconfig: mx6ull: Deselect MX6UL from CONFIG_MX6ULL") CONFIG_MX6ULL does not select CONFIG_MX6UL anymore, so take this into consideration in all the checks for CONFIG_MX6UL. This fixes a boot regression. Reported-by:
Stefan Agner <stefan@agner.ch> Signed-off-by:
Breno Lima <breno.lima@nxp.com> Tested-by:
Jörg Krause <joerg.krause@embedded.rocks>
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