- Jan 17, 2011
-
-
Stefano Babic authored
Signed-off-by:Stefano Babic <sbabic@denx.de>
-
-
-
- Jan 14, 2011
-
-
Kumar Gala authored
Simultaneous FCM and GPCM or UPM operation may erroneously trigger bus monitor timeout. Set timeout to maximum to avoid. Based on a patch from Lan Chunhe <b25806@freescale.com> Signed-off-by:Kumar Gala <galak@kernel.crashing.org>
-
Kumar Gala authored
CoreNet Platform Cache single-bit data error scrubbing will cause data corruption. Disable the feature to workaround the issue. Signed-off-by: -
Kumar Gala authored
CoreNet Platform Cache single-bit tag error scrubbing will cause tag corruption. Disable the feature to workaround the issue. Signed-off-by: -
Kumar Gala authored
CONFIG_SYS_BOOTMAPSZ has been 16M on these boards for some time so we should also allow the kernel image to be up to 16M decompressed. Signed-off-by: -
Kumar Gala authored
Move the parsing of hwconfig to determine if to use spd into common code so we can share it across all boards instead of duplicating it everywhere. Signed-off-by: -
Roy Zang authored
False multi-bit ECC errors will be reported by the eSDHC buffer which can trigger a reset request. We disable all ECC error checking on SDHC. Signed-off-by:
Roy Zang <tie-fei.zang@freescale.com> Signed-off-by:
-
Roy Zang authored
The default value of the SRS, VS18 and VS30 and ADMAS fields in the host controller capabilities register (HOSTCAPBLT) are incorrect. The default of these bits should be zero instead of one. Clear these bits out when we read HOSTCAPBLT. Signed-off-by:
-
Jerry Huang authored
Do not issue a manual asynchronous CMD12. Instead, use a (software) synchronous CMD12 or AUTOCMD12 to abort data transfer. Signed-off-by:
Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by:
-
Li Yang authored
The P2020 has 2 SRIO ports and they are useable on the P2020 DS board. Enable them using the common SRIO init code. Signed-off-by:
Li Yang <leoli@freescale.com> Signed-off-by:
-
Kumar Gala authored
Signed-off-by:
Paul Gortmaker <paul.gortmaker@windriver.com>
-
Kumar Gala authored
Signed-off-by: -
Kumar Gala authored
Add the needed defines and code to utilize the common 8xxx srio init code to setup LAWs and modify device tree if we have SRIO enabled on a board. Signed-off-by: -
Kumar Gala authored
Signed-off-by: -
Kumar Gala authored
Signed-off-by: -
Kumar Gala authored
Signed-off-by: -
Kumar Gala authored
Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO. We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically. We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled. Introduced the following standard defines for board config.h: CONFIG_SYS_SRIO - Chip has SRIO or not CONFIG_SRIO1 - Board has SRIO 1 port available CONFIG_SRIO2 - Board has SRIO 2 port available (where 'n' is the port #) CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup) CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup) [ These mimic what we have for PCI and PCIe controllers ] Signed-off-by:
Wolfgang Denk <wd@denx.de>
-
Peter Tyser authored
This change does the following: - Adds printing of negotiated link width. This information can be useful when debugging PCIe issues. - Makes it optional for boards to implement board_serdes_name(). Previously boards that did not implement it would print unsightly output such as "PCIE1: Connected to <NULL>..." - Rewords the PCIe boot output to reduce line length and to make it clear that the "base address XYZ" value refers to the base address of the internal processor PCIe registers and not a standard PCI BAR value. - Changes "PCIE" output to the standard "PCIe" Before change: PCIE1: connected to <NULL> as Root Complex (base addr ef008000) 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 05 PCIE2: connected to <NULL> as Endpoint (base addr ef009000) PCIE2: Bus 06 - 06 After change: PCIe1: Root Complex of PEX8518 Switch, x4, regs @ 0xef008000 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIe1: Bus 00 - 05 PCIe2: Endpoint of VPX Fabric A, x2, regs @ 0xef009000 PCIe2: Bus 06 - 06 Signed-off-by:
Peter Tyser <ptyser@xes-inc.com> Signed-off-by:
-
Kumar Gala authored
Remove duplicated code in corenet_ds boards and utilize the common fsl_pcie_init_board(). Signed-off-by: -
Kumar Gala authored
Remove duplicated code in SBC8548 board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by:
-
Kumar Gala authored
Remove duplicated code in SBC8641 board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: -
Kumar Gala authored
Remove duplicated code in MPC8610HPCD board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: -
Kumar Gala authored
Remove duplicated code in P1_P2_RDB boards and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: -
Kumar Gala authored
Remove duplicated code in MPC8569MDS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: -
Kumar Gala authored
Remove duplicated code in MPC8568MDS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: -
Kumar Gala authored
Remove duplicated code in TQM 85xx boards and utilize the common fsl_pcie_init_board(). Signed-off-by: -
Kumar Gala authored
Remove duplicated code in MPC8xxx XES boards and utilize the common fsl_pcie_init_board(). Signed-off-by: -
Kumar Gala authored
Remove duplicated code in MPC8548CDS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: -
Kumar Gala authored
Remove duplicated code in MPC8641HPCN board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: -
Kumar Gala authored
Remove duplicated code in MPC8536DS board and utilize the common fsl_pcie_init_board(). Signed-off-by: -
Kumar Gala authored
Remove duplicated code in MPC8544DS board and utilize the common fsl_pcie_init_ctrl(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. We don't use the full fsl_pcie_init_ctrl() since we have to handle PCIE3 specially to setup the additional memory map region and we utilize a single LAW to cover the controller. Signed-off-by: -
Kumar Gala authored
Remove duplicated code in P2020DS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by:
-
Kumar Gala authored
Remove duplicated code in MPC8572DS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by:
Chenhui Zhao <b26998@freescale.com> Signed-off-by:
-
Kumar Gala authored
Since all the PCIe controllers are connected over SERDES on the SoCs we can utilize is_serdes_configured() to determine if a controller is enabled. After which we can setup the ATMUs and LAWs for the controller in a common fashion and allow board code to specify what the controller is connected to for reporting reasons. We also provide a per controller (rather than all) for some systems that may have special requirements. Finally, we refactor the code used by the P1022DS to utilize the new generic code. Based on patch by: Li Yang <leoli@freescale.com> Signed-off-by: -
Kumar Gala authored
Previously we passed in a specifically named struct pci_controller to determine if we had setup the particular PCI bus. Now we can search for the struct so we dont have to depend on the name or the struct being statically allocated. Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct back by searching for it means we can do things like dynamically allocate them or not have to expose the static structures to all users. Signed-off-by:
-
Kumar Gala authored
We set the L1 dache register with a bogus register value. Need to be using 'r3' instead of 'r0'. Reported-by:
John Traill <john.traill@freescale.com> Signed-off-by:
-
Becky Bruce authored
Add spaces to cause the informational prints to line up with the ones from init_func_ram() in board.c. Output now looks like this: .... DRAM: Detected 4096 MB of memory This U-Boot only supports < 4G of DDR You could rebuild it with CONFIG_PHYS_64BIT DDR: 2 GiB (DDR2, 64-bit, CL=5, ECC off) .... The prints from lbc_sdram_init() have also been modified to line line up and changed to start with "LBC SDRAM" instead of the confusing "SDRAM". Signed-off-by:Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by:
-
Becky Bruce authored
This config option is for an erratum workaround; rename it to be more clear. Also, drop it from config files don't need it and were undefining it. Signed-off-by:
-
