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Commit 3b4456ec authored by Roy Zang's avatar Roy Zang Committed by Kumar Gala
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fsl_esdhc: Add the workaround for erratum ESDHC135 (enable on P4080)


The default value of the SRS, VS18 and VS30 and ADMAS fields in the host
controller capabilities register (HOSTCAPBLT) are incorrect. The default
of these bits should be zero instead of one.

Clear these bits out when we read HOSTCAPBLT.

Signed-off-by: default avatarRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent d621da00
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