fsl_esdhc: Add the workaround for erratum ESDHC136 (enable on P4080)

False multi-bit ECC errors will be reported by the eSDHC buffer which
can trigger a reset request.

We disable all ECC error checking on SDHC.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

arch/powerpc/cpu/mpc85xx/cmd_errata.c

@@ -55,6 +55,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #endif
 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135)
 	puts("Work-around for Erratum ESDHC135 enabled\n");
+#endif
+#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC136)
+	puts("Work-around for Erratum ESDHC136 enabled\n");
 #endif
 	return 0;
 }

arch/powerpc/cpu/mpc85xx/cpu_init.c

@@ -394,6 +394,14 @@ int cpu_init_r(void)
 	setup_mp();
 #endif
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC136
+	{
+		void *p;
+		p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
+		setbits_be32(p, 1 << (31 - 14));
+	}
+#endif
+
 #ifdef CONFIG_SYS_LBC_LCRR
 	/*
 	 * Modify the CLKDIV field of LCRR register to improve the writing

include/configs/P4080DS.h

@@ -37,6 +37,7 @@
 
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC136
 
 #define CONFIG_SYS_P4080_ERRATUM_CPU22
 #define CONFIG_SYS_P4080_ERRATUM_SERDES8