- Aug 07, 2018
-
-
Troy Kisky authored
a: add usb hub reset/uart3/uart4/flexcan pins a: keep USB Huawei Modem in reset a: add leds rx active/tx active a: remove printf of board_mmc_init a.h: add cmd_custom to avoid update u-boot warning a: add CONFIG_CMD_GPIO a: remove redundant CONFIG_CMD_GPIO a: verify port in board_ehci_hcd_init a: use boundary.h a: call preboot_keys a: add CONFIG_SPI_FLASH_SPANSION a: add RV4162 rtc on I2C2 a: a_defconfig add CONFIG_BLOCK_CACHE a: use common code for eth init a: eth.c now in common directory a: move misc_init_r/do_kbd to common a: move mmc_init/ dram_init/ overwrite_console/ common_board_init/ splash_screen_prepare/ board_cfb_skip to common a: add CONFIG_SPI_FLASH_GIGADEVICE: to defconfigs a: add a_s512m.cfg a: port to v2018.07 Signed-off-by:
Troy Kisky <troy.kisky@boundarydevices.com> a: update to v2017.01 a: update to v2017.03 a.h: add custom BOOT_TARGET_DEVICES priority Signed-off-by:
Gary Bisson <gary.bisson@boundarydevices.com>
-
Troy Kisky authored
Signed-off-by: -
Troy Kisky authored
Signed-off-by: -
Troy Kisky authored
Signed-off-by: -
Troy Kisky authored
Signed-off-by:
-
- Jul 27, 2018
-
-
Troy Kisky authored
Signed-off-by: -
Troy Kisky authored
Signed-off-by: -
Troy Kisky authored
fbpanel: LVDS666 has NO use cases, why does it even exist? fbpanel: fix MX6SX lvds display bus-width fbpanel.h: lg1280x800(LP101WX1) == hannstar7 fbpanel.h: add ASIT500MA6F5D fbpanel.h: add IMX_VD_A030JN01_YUV720 fbpanel: check for YUYV format fbpanel: add hdmi vga mode fbpanel: add hdmi 480p fbpanel:LSA40AT9001 is a 24 bit panel fbpanel: add IMX_VD50_800_600MR_60 800x600MR@60 fbpanel: fix hdmi 800x600 and LSA40AT9001 pix clocks fbpanel: add IMX_VD38_AUO_B101EW05 fbpanel: add IMX_VD38_DT070BTFT fbpanel: add IMX_VD_LD070WSVGA fbpanel.h: add IMX_VD38_TM070JDHG30 fbpanel: add IMX_VD_1080P60_J (jeida 1080p dual lvds) fbpanel: add tx23d200_24/tx23d200_18 fbpanel.h: add ipu_set_ldb_clock definition fbpanel: add setup_clock to setup pll5_video clock fbpanel: fix qvga clock fbpanel: support clocks for TO1.0 fbpanel: increase tx23d200 to 52 Hz fbpanel: fix setup_clock for imx6sx fbpanel: allow passing i2c addr in macros fbpanel: add LVDS2 individual panel support fbpanel: disable lvds-channel@n if not used fbpanel.h: add VD_INNOLUX_WVGA_M fbpanel: use _detect as function, add itw panels fbpanel: OSD-WSVGA is JEIDA fbpanel: VD_INNOLUX_WXGA_14IN_12V/VD_OSD_WSVGA are 18 bit panels fbpanel.h: add VDF_ macros fbpanel: add VD_AFK1024600A02 fbpanel: only reference lvds-channel@1 if (fb == FB_LVDS2) fbpanel: add VDF_KD024FM fbpanel.h: 10kHz backlight for ASIT500MA6F5D fbpanel: use board_pre_enable fbpanel: add Sexp parsing (SPI/pre_enable/bus,addr/backlight period) fbpanel: deglitch lvds clock fbpanel: only change ldb that is needed and follow EB821 closer fbpanel: create function reparent_lvds by moving code fbpanel: make sure to disable lcd node fbpanel.h: add VD_800X300_565 fbpanel: add FB_LCD2 for imx51 support fbpanel.h: add VD_TFC_A9700LTWV35TC_C1 fbpanel: fix cmd_lvds2 when lvds2 is primary fbpanel: use FB_COUNT instead of hardcoded 4, it is 5 now fbpanel: add ND-070PCAP-1024x600 fbpanel: include mx53 support fbpanel: add NeonTouch640x240 using IPU clock fbpanel: 800x300rgb565 uses internal clock for Wince fbpanel: add board_video_enable callback fbpanel: add imx7d/imx6sx support fbpanel: add VD_M101NWWB fbpanel: add FBF_BKLIT_LOW_ACTIVE/FBF_BKLIT_DTB to modify dtb backlight levels fbpanel: protect from divide by 0 errors fbpanel: add DV210FBM 1920x132 display Signed-off-by:
-
Troy Kisky authored
Signed-off-by: -
Troy Kisky authored
mx5: lowlevel_init: disable IPU handshake for i.mx53 mx5: lowlevel_init: Turn on internal oscillator mx5: lowlevel_init: minor cleanup of init_l2cc mx5: lowlevel_init: use \r_zero for r4 mx5: lowlevel_init: use \r_ccm where CCM addresses are referenced mx5: lowlevel_init: use macro divisor_change_wait mx5: lowlevel_init: use \r_plln mx5: lowlevel_init: prevent glitches mx5: lowlevel_init: pll startup change mx5: lowlevel_init: add erratum 709718, aips change to allow devregs to work mx5: lowlevel_init: invalidate L1 cache mx5: lowlevel_init: use parameters for init_aips/init_m4if mx5: lowlevel_init: merge mx51/mx53 code mx5: lowlevel_init: add macro orr_mx51_tape2_or_lower mx5: lowlevel_init: use iim srev instead of undocumented register Signed-off-by: -
Troy Kisky authored
Signed-off-by: -
Troy Kisky authored
Signed-off-by: -
Troy Kisky authored
Signed-off-by: -
Troy Kisky authored
Signed-off-by: -
Troy Kisky authored
Signed-off-by: -
Ye.Li authored
To resolve USB camera bandwidth issue, the patch sets recommended AQoS setting from IC team value for peripheral and only on imx6qp. The address is: 0xbb0608, the value is: 0x80000201 Signed-off-by:Ye.Li <B37916@freescale.com> (cherry picked from commit d00e9400bfbfb097ab5b0b26fae92db3dc1dd047)
-
Ye.Li authored
Since i.MX6DQP has fixed the L2 cache issue, enable the double line fill feature to provide better performance. Signed-off-by: -
Troy Kisky authored
-
Troy Kisky authored
-
Eric Nelson authored
The use of the i.MX6 fuses is useful even on designs without the FEC ethernet controller. Allow boards to request the routine through CONFIG_FEC_MAC_FUSE. Signed-off-by:Eric Nelson <eric.nelson@boundarydevices.com>
-
Troy Kisky authored
-
- Jul 12, 2018
-
-
Troy Kisky authored
Signed-off-by:
-
- Jul 10, 2018
-
-
Troy Kisky authored
nitrogen8m: add ddr/ddr_memory_map.h nitrogen8m: u-boot update changes nitrogen8m: turn off cameras nitrogen8m: cameras reset/pwrdn use ODE This limits the high level current to the pullup resistor. Signed-off-by:
-
Troy Kisky authored
Signed-off-by: -
Troy Kisky authored
Signed-off-by: -
Ye Li authored
Add 400Mhz, 600Mhz and 800Mhz frequencies for dram pll init function to support DDR3L/DDR4/LPDDR4. Signed-off-by:Ye Li <ye.li@nxp.com>
-
Ye.Li authored
Add gis module, current gis is support vadc input. Add power down function to lcdif driver. Signed-off-by:
Sandor Yu <R01008@freescale.com> Signed-off-by:
-
Troy Kisky authored
Signed-off-by: -
Ye Li authored
Checks whether the HDMI FW is running before initialize the HDMI display. So that for cases like mfgtool and imx-boot image without HDMI FW, the u-boot won't be blocked. Signed-off-by: -
Oliver Brown authored
Adding basic HDMI support for i.MX8 for splash screen. Signed-off-by:Oliver Brown <oliver.brown@nxp.com>
-
Ye Li authored
Need to pass total 5 arguments for SIP HAB call, so update the interface to add new argument. Signed-off-by: -
Ye Li authored
ATF will power off all PUs at default, so for USB, we enable its PU power for both host and device modes in board_usb_init and disable the power when usb is stop in board_usb_cleanup. Signed-off-by:
Li Jun <jun.li@nxp.com>
-
- Jul 02, 2018
-
-
Tom Rini authored
The various Aries Embedded boards have been orphaned for a year and no one has come forward to take care of them. Remove. Signed-off-by:Tom Rini <trini@konsulko.com>
-
- Jun 30, 2018
-
-
Fabio Estevam authored
On a 4.18-rc1 kernel the following warning is seen on i.MX51 and i.MX53: CPU0: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable Select the ARM_CORTEX_A8_CVE_2017_5715 workaround for i.MX51/i.MX53 to fix the problem. With this patch applied the kernel reports: CPU0: Spectre v2: using BPIALL workaround Signed-off-by:Fabio Estevam <fabio.estevam@nxp.com>
-
- Jun 19, 2018
-
-
Michal Simek authored
cpu_cmd() is reading cpu number via simple_strtoul() which is always unsigned type. Platform code implementations are not expecting that nr can be negative and there is not checking in the code for that too. This patch is using u32 type for cpu number to make sure that platform code get proper value range. Signed-off-by:Michal Simek <michal.simek@xilinx.com>
-
- Jun 18, 2018
-
-
Ye Li authored
According to the Cortex-A7 TRM, for ACTLR.SMP bit "You must ensure this bit is set to 1 before the caches and MMU are enabled, or any cache and TLB maintenance operations are performed". ROM sets this bit in normal boot flow, but when in serial download mode, it is not set. Here we add it in u-boot as a common flow for all i.MX cortex-a7 platforms, including mx7d, mx6ul/ull and mx7ulp. Signed-off-by:
-
- May 18, 2018
-
-
Lukasz Majewski authored
This commit adds support for DDC and HSC boards from K+P in u-boot. Console output: U-Boot 2018.05-rc2-00090-g752b7ed6f9 (Apr 26 2018 - 14:24:24 +0200) CPU: Freescale i.MX53 rev2.1 at 800 MHz Reset cause: WDOG Model: K+P iMX53 DRAM: 512 MiB MMC: FSL_SDHC: 0 Loading Environment from MMC... OK In: serial Out: serial Err: serial Module EEPROM: ID: TQMa53-CB.0401 SN: 63152762 MAC: 00:0b:64:03:14:2a BBoard:40x0 Rev:10 Net: eth0: ethernet@63fec000 Hit any key to stop autoboot: 0 Signed-off-by:Lukasz Majewski <lukma@denx.de>
-
Jagan Teki authored
MX6DL Mamoj boards has Freescale PFUZE100 PMIC, add support for it through DM_PMIC dt definition. pmic log: Reviewed-by:
Stefano Babic <sbabic@denx.de> ======== => pmic list | Name | Parent name | Parent uclass @ seq | pfuze100@08 | i2c@021f8000 | i2c @ 3 => pmic dev pfuze100@08 dev: 0 @ pfuze100@08 => pmic dump Dump pmic: pfuze100@08 registers 0x00: 10 00 00 21 00 01 3f 01 00 7f 00 00 00 00 00 81 0x10: 00 00 3f 00 00 00 00 00 00 00 00 10 00 00 00 00 0x20: 2b 2b 2b 08 c4 00 00 00 00 00 00 00 00 00 2b 2b 0x30: 2b 08 c4 00 00 72 72 72 08 d4 00 00 2c 2c 2c 08 0x40: e4 00 00 2c 2c 2c 08 e4 00 00 6f 6f 6f 08 f4 00 0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0x60: 00 00 00 00 00 00 48 00 00 00 10 06 1e 1e 17 10 0x70: 1a 1f 00 00 00 00 00 00 00 00 00 00 00 00 00 Signed-off-by:
Jagan Teki <jagan@amarulasolutions.com> Signed-off-by:
Simone CIANNI <simone.cianni@bticino.it> Signed-off-by:
Raffaele RECALCATI <raffaele.recalcati@bticino.it>
-
Jagan Teki authored
i.MX6DL Mamoj has i2c3 and i2c4 buses, add support through DM_I2C with dt definition. i2c log: Reviewed-by:
-
Jagan Teki authored
Add initial support for i.MX6DL BTicino Mamoj board. Mamoh board added: - SPL - SPL_DM - SPL_OF_CONTROL - DM for U-Boot proper - OF_CONTROL for U-Boot proper - eMMC - FEC - Boot from eMMC - Boot from USB SDP Signed-off-by:
-
