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Commit e7dc31a8 authored by Troy Kisky's avatar Troy Kisky
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video_common: fix compile errors

parent 867eaf06
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......@@ -146,21 +146,23 @@ void imx8m_create_color_bar(void *start_address,
static void imx8m_set_clocks(int apb_clk, int b_clk, int hdmi_core_clk,
int p_clk, int rtr_clk)
{
struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR;
if (b_clk == 800) {
/* b_clk: bus_clk_root(4) sel 2nd input source and
pre_div to 0; output should be 800M */
reg32_write(CCM_BUS_CLK_ROOT_GEN_TAGET_CLR(4),
reg32_write(&ccm_reg->bus_root[4].target_root_clr,
(0x7 << 24) | (0x7 << 16));
reg32_write(CCM_BUS_CLK_ROOT_GEN_TAGET_SET(4), (0x2 << 24));
reg32_write(&ccm_reg->bus_root[4].target_root_set, (0x2 << 24));
} else {
printf("b_clk does not match a supported frequency");
}
if (rtr_clk == 400) {
/* rtr_clk: bus_clk_root(6) sel 1st input source
and pre_div to 1; output should be 400M */
reg32_write(CCM_BUS_CLK_ROOT_GEN_TAGET_CLR(6),
reg32_write(&ccm_reg->bus_root[6].target_root_clr,
(0x7 << 24) | (0x7 << 16));
reg32_write(CCM_BUS_CLK_ROOT_GEN_TAGET_SET(6),
reg32_write(&ccm_reg->bus_root[6].target_root_set,
(0x1 << 24) | (0x1 << 16));
} else {
debug("rtr_clk does not match a supported frequency");
......@@ -171,9 +173,9 @@ static void imx8m_set_clocks(int apb_clk, int b_clk, int hdmi_core_clk,
if (hdmi_core_clk == 200) {
/* hdmi_core_clk: ip_clk_root(69) sel 1st input source and
pre_div to 0 */
reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(69),
reg32_write(&ccm_reg->bus_root[69].target_root_clr,
(0x7 << 24) | (0x7 << 16));
reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(69), (0x1 << 24));
reg32_write(&ccm_reg->bus_root[69].target_root_set, (0x1 << 24));
g_hdmi_core_clock = 200000000;
} else {
debug("hdmi_core_clk does not match a supported frequency");
......@@ -185,39 +187,39 @@ static void imx8m_set_clocks(int apb_clk, int b_clk, int hdmi_core_clk,
if (p_clk == 27) {
/* p_clk: ip_clk_root(9) sel 1st input source and
pre_div to 1; post_div to 5, output 100M */
reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(9),
reg32_write(&ccm_reg->bus_root[9].target_root_clr,
(0x7 << 24) | (0x7 << 16));
reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(9),
reg32_write(&ccm_reg->bus_root[9].target_root_set,
(0x1 << 24) | (29 << 16));
} else if (p_clk == 100) {
/* p_clk: ip_clk_root(9) sel 1st input source and
pre_div to 1; post_div to 5, output 100M */
reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(9),
reg32_write(&ccm_reg->bus_root[9].target_root_clr,
(0x7 << 24) | (0x7 << 16));
reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(9),
reg32_write(&ccm_reg->bus_root[9].target_root_set,
(0x1 << 24) | (0x5 << 16));
} else if (p_clk == 120) {
/* p_clk: ip_clk_root(9) sel 1st input source and
pre_div to 1; post_div to 4, output 120M */
reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(9),
reg32_write(&ccm_reg->bus_root[9].target_root_clr,
(0x7 << 24) | (0x7 << 16));
reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(9),
reg32_write(&ccm_reg->bus_root[9].target_root_set,
(0x1 << 24) | (0x4 << 16));
} else if (p_clk == 200) {
/* I added this to speed up the pixel clock and
get frames out faster. may need to adjust this.
*/
reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(9),
reg32_write(&ccm_reg->bus_root[9].target_root_clr,
(0x7 << 24) | (0x7 << 16));
reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(9),
reg32_write(&ccm_reg->bus_root[9].target_root_set,
(0x4 << 24) | (0x3 << 16)); /*for emu use 800 / 4 */
} else if (p_clk == 400) {
/* I added this to speed up the pixel clock and
get frames out faster. may need to adjust this.
*/
reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(9),
reg32_write(&ccm_reg->bus_root[9].target_root_clr,
(0x7 << 24) | (0x7 << 16));
reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(9),
reg32_write(&ccm_reg->bus_root[9].target_root_set,
(0x4 << 24) | (0x1 << 16)); /*for emu use 800 / 2 */
} else if (p_clk == 40) { /* Do not reprogram, will get 40MHz */
} else {
......
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