Skip to content
Snippets Groups Projects
  1. Nov 09, 2013
    • Paul Burton's avatar
      pcnet: enable the NOUFLO feature · 62715a2c
      Paul Burton authored
      
      On relatively slow boards (such as the MIPS Malta with an FPGA core
      card) it can be extremely common for transmits to underflow - to the
      point where it appears they simply do not work at all. Setting the
      NOUFLO bit causes the ethernet controller to not begin transmission on
      the wire until a transmit start point is reached. Setting that transmit
      start point to the full packet will cause the controller to only
      transmit the packet once it has buffered it entirely thus preventing any
      transmit underflows from occuring and allowing the controller to
      function on slower boards.
      
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      62715a2c
    • Paul Burton's avatar
      pcnet: add cache flushing & invalidation · f3ac866c
      Paul Burton authored
      
      Ensure that the view of memory from the CPU & the ethernet controller is
      coherent at the various points where they exchange data. This prevents
      stale data from being transmitted or received, and prevents the driver
      from getting stuck waiting for the ethernet controller to update
      descriptors when in reality it has but the old values are being read
      from cache.
      
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      f3ac866c
    • Paul Burton's avatar
      pcnet: s/le16_to_cpu/cpu_to_le16/ in pcnet_send · a9540041
      Paul Burton authored
      
      This should cause no change to the generated code, but is semantically
      correct.
      
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      a9540041
    • Paul Burton's avatar
      pcnet: code style cleanup · 6011dabd
      Paul Burton authored
      
      Fix up the code to match Documentation/CodingStyle. This is mostly
      removing extraneous spaces.
      
      No functional change is intended.
      
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      6011dabd
    • Paul Burton's avatar
      mips32: detect L1 cache sizes if they're not defined · fa476f75
      Paul Burton authored
      
      For boards such as the MIPS Malta with an FPGA core card it is desirable
      to be able to detect the L1 cache sizes at runtime, since they are not
      dependant upon the board but on the FPGA bitstream in use. This patch
      performs that detection when the CONFIG_SYS_[DI]CACHE_SIZE macros are
      not defined by the board configuration. In cases where the sizes are
      detected this patch also removes the restriction that the I-cache &
      D-cache line sizes must be the same, as this is not necessarily true.
      
      If the cache sizes are defined by a configuration then they will be
      hardcoded as before, so this patch will not add overhead to such
      boards.
      
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      fa476f75
  2. Nov 08, 2013
Loading