omap_hsmmc.c

		mmc_read_data(mmc_base,	data->dest,
				data->blocksize * data->blocks);
	} else if (data && (data->flags & MMC_DATA_WRITE)) {
		mmc_write_data(mmc_base, data->src,
				data->blocksize * data->blocks);
	}
	return 0;
}

static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
{
	unsigned int *output_buf = (unsigned int *)buf;
	unsigned int mmc_stat;
	unsigned int count;

	/*
	 * Start Polled Read
	 */
	count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
	count /= 4;

	while (size) {
		ulong start = get_timer(0);
		do {
			mmc_stat = readl(&mmc_base->stat);
			if (get_timer(0) - start > MAX_RETRY_MS) {
				printf("%s: timedout waiting for status!\n",
						__func__);
				return -ETIMEDOUT;
			}
		} while (mmc_stat == 0);

		if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
			mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);

		if ((mmc_stat & ERRI_MASK) != 0)
			return 1;

		if (mmc_stat & BRR_MASK) {
			unsigned int k;

			writel(readl(&mmc_base->stat) | BRR_MASK,
				&mmc_base->stat);
			for (k = 0; k < count; k++) {
				*output_buf = readl(&mmc_base->data);
				output_buf++;
			}
			size -= (count*4);
		}

		if (mmc_stat & BWR_MASK)
			writel(readl(&mmc_base->stat) | BWR_MASK,
				&mmc_base->stat);

		if (mmc_stat & TC_MASK) {
			writel(readl(&mmc_base->stat) | TC_MASK,
				&mmc_base->stat);
			break;
		}
	}
	return 0;
}

static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
				unsigned int size)
{
	unsigned int *input_buf = (unsigned int *)buf;
	unsigned int mmc_stat;
	unsigned int count;

	/*
	 * Start Polled Write
	 */
	count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
	count /= 4;

	while (size) {
		ulong start = get_timer(0);
		do {
			mmc_stat = readl(&mmc_base->stat);
			if (get_timer(0) - start > MAX_RETRY_MS) {
				printf("%s: timedout waiting for status!\n",
						__func__);
				return -ETIMEDOUT;
			}
		} while (mmc_stat == 0);

		if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
			mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);

		if ((mmc_stat & ERRI_MASK) != 0)
			return 1;

		if (mmc_stat & BWR_MASK) {
			unsigned int k;

			writel(readl(&mmc_base->stat) | BWR_MASK,
					&mmc_base->stat);
			for (k = 0; k < count; k++) {
				writel(*input_buf, &mmc_base->data);
				input_buf++;
			}
			size -= (count*4);
		}

		if (mmc_stat & BRR_MASK)
			writel(readl(&mmc_base->stat) | BRR_MASK,
				&mmc_base->stat);

		if (mmc_stat & TC_MASK) {
			writel(readl(&mmc_base->stat) | TC_MASK,
				&mmc_base->stat);
			break;
		}
	}
	return 0;
}

static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
{
	writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
}

static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
{
	writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
}

static void omap_hsmmc_set_clock(struct mmc *mmc)
{
	struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
	struct hsmmc *mmc_base;
	unsigned int dsor = 0;
	ulong start;

	mmc_base = priv->base_addr;
	omap_hsmmc_stop_clock(mmc_base);

	/* TODO: Is setting DTO required here? */
	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
		    (ICE_STOP | DTO_15THDTO));

	if (mmc->clock != 0) {
		dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
		if (dsor > CLKD_MAX)
			dsor = CLKD_MAX;
	} else {
		dsor = CLKD_MAX;
	}

	mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
		    (dsor << CLKD_OFFSET) | ICE_OSCILLATE);

	start = get_timer(0);
	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for ics!\n", __func__);
			return;
		}
	}

	priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor;
	mmc->clock = priv->clock;
	omap_hsmmc_start_clock(mmc_base);
}

static void omap_hsmmc_set_bus_width(struct mmc *mmc)
{
	struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
	struct hsmmc *mmc_base;

	mmc_base = priv->base_addr;
	/* configue bus width */
	switch (mmc->bus_width) {
	case 8:
		writel(readl(&mmc_base->con) | DTW_8_BITMODE,
			&mmc_base->con);
		break;

	case 4:
		writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
			&mmc_base->con);
		writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
			&mmc_base->hctl);
		break;

	case 1:
	default:
		writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
			&mmc_base->con);
		writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
			&mmc_base->hctl);
		break;
	}

	priv->bus_width = mmc->bus_width;
}

#if !CONFIG_IS_ENABLED(DM_MMC)
static int omap_hsmmc_set_ios(struct mmc *mmc)
{
	struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
#else
static int omap_hsmmc_set_ios(struct udevice *dev)
{
	struct omap_hsmmc_data *priv = dev_get_priv(dev);
	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	struct mmc *mmc = upriv->mmc;
#endif

	if (priv->bus_width != mmc->bus_width)
		omap_hsmmc_set_bus_width(mmc);

	if (priv->clock != mmc->clock)
		omap_hsmmc_set_clock(mmc);

#if CONFIG_IS_ENABLED(DM_MMC)
	if (priv->mode != mmc->selected_mode)
		omap_hsmmc_set_timing(mmc);
#endif
	return 0;
}

#ifdef OMAP_HSMMC_USE_GPIO
#if CONFIG_IS_ENABLED(DM_MMC)
static int omap_hsmmc_getcd(struct udevice *dev)
{
	struct omap_hsmmc_data *priv = dev_get_priv(dev);
	int value;

	value = dm_gpio_get_value(&priv->cd_gpio);
	/* if no CD return as 1 */
	if (value < 0)
		return 1;

	if (priv->cd_inverted)
		return !value;
	return value;
}

static int omap_hsmmc_getwp(struct udevice *dev)
{
	struct omap_hsmmc_data *priv = dev_get_priv(dev);
	int value;

	value = dm_gpio_get_value(&priv->wp_gpio);
	/* if no WP return as 0 */
	if (value < 0)
		return 0;
	return value;
}
#else
static int omap_hsmmc_getcd(struct mmc *mmc)
{
	struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
	int cd_gpio;

	/* if no CD return as 1 */
	cd_gpio = priv->cd_gpio;
	if (cd_gpio < 0)
		return 1;

	/* NOTE: assumes card detect signal is active-low */
	return !gpio_get_value(cd_gpio);
}

static int omap_hsmmc_getwp(struct mmc *mmc)
{
	struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
	int wp_gpio;

	/* if no WP return as 0 */
	wp_gpio = priv->wp_gpio;
	if (wp_gpio < 0)
		return 0;

	/* NOTE: assumes write protect signal is active-high */
	return gpio_get_value(wp_gpio);
}
#endif
#endif

#if CONFIG_IS_ENABLED(DM_MMC)
static const struct dm_mmc_ops omap_hsmmc_ops = {
	.send_cmd	= omap_hsmmc_send_cmd,
	.set_ios	= omap_hsmmc_set_ios,
#ifdef OMAP_HSMMC_USE_GPIO
	.get_cd		= omap_hsmmc_getcd,
	.get_wp		= omap_hsmmc_getwp,
#endif
#ifdef MMC_SUPPORTS_TUNING
	.execute_tuning = omap_hsmmc_execute_tuning,
#endif
	.send_init_stream	= omap_hsmmc_send_init_stream,
};
#else
static const struct mmc_ops omap_hsmmc_ops = {
	.send_cmd	= omap_hsmmc_send_cmd,
	.set_ios	= omap_hsmmc_set_ios,
	.init		= omap_hsmmc_init_setup,
#ifdef OMAP_HSMMC_USE_GPIO
	.getcd		= omap_hsmmc_getcd,
	.getwp		= omap_hsmmc_getwp,
#endif
};
#endif

#if !CONFIG_IS_ENABLED(DM_MMC)
int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
		int wp_gpio)
{
	struct mmc *mmc;
	struct omap_hsmmc_data *priv;
	struct mmc_config *cfg;
	uint host_caps_val;

	priv = malloc(sizeof(*priv));
	if (priv == NULL)
		return -1;

	host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;

	switch (dev_index) {
	case 0:
		priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
		break;
#ifdef OMAP_HSMMC2_BASE
	case 1:
		priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
	defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
	defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
		defined(CONFIG_HSMMC2_8BIT)
		/* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
		host_caps_val |= MMC_MODE_8BIT;
#endif
		break;
#endif
#ifdef OMAP_HSMMC3_BASE
	case 2:
		priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
#if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
		/* Enable 8-bit interface for eMMC on DRA7XX */
		host_caps_val |= MMC_MODE_8BIT;
#endif
		break;
#endif
	default:
		priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
		return 1;
	}
#ifdef OMAP_HSMMC_USE_GPIO
	/* on error gpio values are set to -1, which is what we want */
	priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
	priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
#endif

	cfg = &priv->cfg;

	cfg->name = "OMAP SD/MMC";
	cfg->ops = &omap_hsmmc_ops;

	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
	cfg->host_caps = host_caps_val & ~host_caps_mask;

	cfg->f_min = 400000;

	if (f_max != 0)
		cfg->f_max = f_max;
	else {
		if (cfg->host_caps & MMC_MODE_HS) {
			if (cfg->host_caps & MMC_MODE_HS_52MHz)
				cfg->f_max = 52000000;
			else
				cfg->f_max = 26000000;
		} else
			cfg->f_max = 20000000;
	}

	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;

#if defined(CONFIG_OMAP34XX)
	/*
	 * Silicon revs 2.1 and older do not support multiblock transfers.
	 */
	if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
		cfg->b_max = 1;
#endif

	mmc = mmc_create(cfg, priv);
	if (mmc == NULL)
		return -1;

	return 0;
}
#else

#ifdef CONFIG_IODELAY_RECALIBRATION
static struct pad_conf_entry *
omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
{
	int index = 0;
	struct pad_conf_entry *padconf;

	padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count);
	if (!padconf) {
		debug("failed to allocate memory\n");
		return 0;
	}

	while (index < count) {
		padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]);
		padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]);
		index++;
	}

	return padconf;
}

static struct iodelay_cfg_entry *
omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
{
	int index = 0;
	struct iodelay_cfg_entry *iodelay;

	iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count);
	if (!iodelay) {
		debug("failed to allocate memory\n");
		return 0;
	}

	while (index < count) {
		iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]);
		iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]);
		iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]);
		index++;
	}

	return iodelay;
}

static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32  phandle,
						   const char *name, int *len)
{
	const void *fdt = gd->fdt_blob;
	int offset;
	const fdt32_t *pinctrl;

	offset = fdt_node_offset_by_phandle(fdt, phandle);
	if (offset < 0) {
		debug("failed to get pinctrl node %s.\n",
		      fdt_strerror(offset));
		return 0;
	}

	pinctrl = fdt_getprop(fdt, offset, name, len);
	if (!pinctrl) {
		debug("failed to get property %s\n", name);
		return 0;
	}

	return pinctrl;
}

static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc,
						char *prop_name)
{
	const void *fdt = gd->fdt_blob;
	const __be32 *phandle;
	int node = dev_of_offset(mmc->dev);

	phandle = fdt_getprop(fdt, node, prop_name, NULL);
	if (!phandle) {
		debug("failed to get property %s\n", prop_name);
		return 0;
	}

	return fdt32_to_cpu(*phandle);
}

static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc,
					       char *prop_name)
{
	const void *fdt = gd->fdt_blob;
	const __be32 *phandle;
	int len;
	int count;
	int node = dev_of_offset(mmc->dev);

	phandle = fdt_getprop(fdt, node, prop_name, &len);
	if (!phandle) {
		debug("failed to get property %s\n", prop_name);
		return 0;
	}

	/* No manual mode iodelay values if count < 2 */
	count = len / sizeof(*phandle);
	if (count < 2)
		return 0;

	return fdt32_to_cpu(*(phandle + 1));
}

static struct pad_conf_entry *
omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
{
	int len;
	int count;
	struct pad_conf_entry *padconf;
	u32 phandle;
	const fdt32_t *pinctrl;

	phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
	if (!phandle)
		return ERR_PTR(-EINVAL);

	pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
					       &len);
	if (!pinctrl)
		return ERR_PTR(-EINVAL);

	count = (len / sizeof(*pinctrl)) / 2;
	padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
	if (!padconf)
		return ERR_PTR(-EINVAL);

	*npads = count;

	return padconf;
}

static struct iodelay_cfg_entry *
omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
{
	int len;
	int count;
	struct iodelay_cfg_entry *iodelay;
	u32 phandle;
	const fdt32_t *pinctrl;

	phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
	/* Not all modes have manual mode iodelay values. So its not fatal */
	if (!phandle)
		return 0;

	pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
					       &len);
	if (!pinctrl)
		return ERR_PTR(-EINVAL);

	count = (len / sizeof(*pinctrl)) / 3;
	iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
	if (!iodelay)
		return ERR_PTR(-EINVAL);

	*niodelay = count;

	return iodelay;
}

static struct omap_hsmmc_pinctrl_state *
omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
{
	int index;
	int npads = 0;
	int niodelays = 0;
	const void *fdt = gd->fdt_blob;
	int node = dev_of_offset(mmc->dev);
	char prop_name[11];
	struct omap_hsmmc_pinctrl_state *pinctrl_state;

	pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
			 malloc(sizeof(*pinctrl_state));
	if (!pinctrl_state) {
		debug("failed to allocate memory\n");
		return 0;
	}

	index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
	if (index < 0) {
		debug("fail to find %s mode %s\n", mode, fdt_strerror(index));
		goto err_pinctrl_state;
	}

	sprintf(prop_name, "pinctrl-%d", index);

	pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
							 &npads);
	if (IS_ERR(pinctrl_state->padconf))
		goto err_pinctrl_state;
	pinctrl_state->npads = npads;

	pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
							&niodelays);
	if (IS_ERR(pinctrl_state->iodelay))
		goto err_padconf;
	pinctrl_state->niodelays = niodelays;

	return pinctrl_state;

err_padconf:
	kfree(pinctrl_state->padconf);

err_pinctrl_state:
	kfree(pinctrl_state);
	return 0;
}

#define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional)		\
	do {								\
		struct omap_hsmmc_pinctrl_state *s = NULL;		\
		char str[20];						\
		if (!(cfg->host_caps & capmask))			\
			break;						\
									\
		if (priv->hw_rev) {					\
			sprintf(str, "%s-%s", #mode, priv->hw_rev);	\
			s = omap_hsmmc_get_pinctrl_by_mode(mmc, str);	\
		}							\
									\
		if (!s)							\
			s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode);	\
									\
		if (!s && !optional) {					\
			debug("%s: no pinctrl for %s\n",		\
			      mmc->dev->name, #mode);			\
			cfg->host_caps &= ~(capmask);			\
		} else {						\
			priv->mode##_pinctrl_state = s;			\
		}							\
	} while (0)

static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
{
	struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
	struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
	struct omap_hsmmc_pinctrl_state *default_pinctrl;

	if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
		return 0;

	default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
	if (!default_pinctrl) {
		printf("no pinctrl state for default mode\n");
		return -EINVAL;
	}

	priv->default_pinctrl_state = default_pinctrl;

	OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false);
	OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false);
	OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false);
	OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false);
	OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false);

	OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false);
	OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false);
	OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true);

	return 0;
}
#endif

#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
#ifdef CONFIG_OMAP54XX
__weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
{
	return NULL;
}
#endif

static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
{
	struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
	struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);

	struct mmc_config *cfg = &plat->cfg;
#ifdef CONFIG_OMAP54XX
	const struct mmc_platform_fixups *fixups;
#endif
	const void *fdt = gd->fdt_blob;
	int node = dev_of_offset(dev);
	int ret;

	plat->base_addr = map_physmem(devfdt_get_addr(dev),
				      sizeof(struct hsmmc *),
				      MAP_NOCACHE);

	ret = mmc_of_parse(dev, cfg);
	if (ret < 0)
		return ret;

	cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
	cfg->f_min = 400000;
	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
	if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
		plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
	if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
		plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
	if (of_data)
		plat->controller_flags |= of_data->controller_flags;

#ifdef CONFIG_OMAP54XX
	fixups = platform_fixups_mmc(devfdt_get_addr(dev));
	if (fixups) {
		plat->hw_rev = fixups->hw_rev;
		cfg->host_caps &= ~fixups->unsupported_caps;
		cfg->f_max = fixups->max_freq;
	}
#endif

#ifdef OMAP_HSMMC_USE_GPIO
	plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
#endif

	return 0;
}
#endif

#ifdef CONFIG_BLK

static int omap_hsmmc_bind(struct udevice *dev)
{
	struct omap_hsmmc_plat *plat = dev_get_platdata(dev);

	return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
#endif
static int omap_hsmmc_probe(struct udevice *dev)
{
	struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	struct omap_hsmmc_data *priv = dev_get_priv(dev);
	struct mmc_config *cfg = &plat->cfg;
	struct mmc *mmc;
#ifdef CONFIG_IODELAY_RECALIBRATION
	int ret;
#endif

	cfg->name = "OMAP SD/MMC";
	priv->base_addr = plat->base_addr;
	priv->controller_flags = plat->controller_flags;
	priv->hw_rev = plat->hw_rev;
#ifdef OMAP_HSMMC_USE_GPIO
	priv->cd_inverted = plat->cd_inverted;
#endif

#ifdef CONFIG_BLK
	mmc = &plat->mmc;
#else
	mmc = mmc_create(cfg, priv);
	if (mmc == NULL)
		return -1;
#endif

#if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL)
	gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
	gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
#endif

	mmc->dev = dev;
	upriv->mmc = mmc;

#ifdef CONFIG_IODELAY_RECALIBRATION
	ret = omap_hsmmc_get_pinctrl_state(mmc);
	/*
	 * disable high speed modes for the platforms that require IO delay
	 * and for which we don't have this information
	 */
	if ((ret < 0) &&
	    (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
		priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
		cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
				    UHS_CAPS);
	}
#endif

	return omap_hsmmc_init_setup(mmc);
}

#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)

static const struct omap_mmc_of_data dra7_mmc_of_data = {
	.controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
};

static const struct udevice_id omap_hsmmc_ids[] = {
	{ .compatible = "ti,omap3-hsmmc" },
	{ .compatible = "ti,omap4-hsmmc" },
	{ .compatible = "ti,am33xx-hsmmc" },
	{ .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
	{ }
};
#endif

U_BOOT_DRIVER(omap_hsmmc) = {
	.name	= "omap_hsmmc",
	.id	= UCLASS_MMC,
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
	.of_match = omap_hsmmc_ids,
	.ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
	.platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
#endif
#ifdef CONFIG_BLK
	.bind = omap_hsmmc_bind,
#endif
	.ops = &omap_hsmmc_ops,
	.probe	= omap_hsmmc_probe,
	.priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
	.flags	= DM_FLAG_PRE_RELOC,
};
#endif