Fix ecp5_evn clock

The system clock was driven directly while it should be driven by the PLL.

Turn litex_boards.community into module

Add ECP5 Evaluation Board

Exact PLL clock can be derived from U1 12 Mhz or X5 50 Mhz clock.

- use 1e9/freq for default_clk_period
- add default serial on tinyfpga_bx
- use S6PLL on minispartan6
- add SPIFlash pins on versa_ecp5

community: Add TrellisBoard

Signed-off-by: David Shah <dave@ds0.me>

Turn litex_boards.partner into module

Add litex_boards package to setup.py

Add fomu target

The evt platform has a different naming scheme from the other two
versions of Fomu.

This harmonises the naming of the rgb_led pads between all of the Fomu
variants.

Signed-off-by: Sean Cross <sean@xobs.io>

The `fomu` target represents a generic target that supports the Fomu
48 MHz crystal, with or without a PLL.

It does not yet include a BaseSoC, since that requires USB and
up5kspram, neither of which are present yet.

Signed-off-by: Sean Cross <sean@xobs.io>

These get generated whenever one of these boards are used, which can
cause issues when this repo is used as a submodule.

Signed-off-by: Sean Cross <sean@xobs.io>

Add fomu platform definitions

Review feedback - rename dvt to pvt - remove serial from both pvt and hacker - remove NC spi wp and hold pins from hacker - remove spiflash4x as pins are NC Added links to schematic/cad data

Update @mithro fomu platform defs from @xobs foboot and try to make them all match the litex style a little more