Merge pull request #13 from DurandA/patch-1

Fix ecp5_evn clock

Merge pull request #13 from DurandA/patch-1
596a8540 · enjoy-digital · GitHub · e31360b1 · 618f41bb · 596a8540
Unverified Commit 596a8540 authored 5 years ago by enjoy-digital Committed by GitHub 5 years ago
--- a/litex_boards/community/targets/ecp5_evn.py
+++ b/litex_boards/community/targets/ecp5_evn.py
@@ -39,7 +39,6 @@ class _CRG(Module):
        pll.register_clkin(clk, x5_clk_freq or 12e6)
        pll.create_clkout(self.cd_sys, sys_clk_freq)
        self.specials += AsyncResetSynchronizer(self.cd_sys, ~rst_n)
-        self.comb += self.cd_sys.clk.eq(clk)

 # BaseSoC ------------------------------------------------------------------------------------------