Otherwise break retro-compat on external design importing CRG without passing this new parameter.

Signed-off-by: Karol Gugala <kgugala@antmicro.com>

Signed-off-by: Karol Gugala <kgugala@antmicro.com>

- main_ram mem_map is now directly used by add_sdram when origin is None.
- max_sdram_size/min_l2_data_width are no longer exposed as targets arguments this can
still be used enforced directly in the few cases it is useful.

boards: Add Vendor prefix to platforms/targets name when useful and when multiple boards from the same vendor. (With Retro-Compat on the imports).

targets: Switch to soc_core_args/soc_core_argdict (instead of soc_sdram that is now deprecated, but still supported for now).

Then adds jtagbone for arty.  I have tested with the following
litex_server and it seems to work fine.

  litex_server --jtag --jtag-config openocd_xc7_ft2232.cfg

Note, the jtagbone and etherbone may be mutually exclusive, but I am not
sure how to define that in the args.

The default stays with the Digilent/Antmicro layout, but the user can
optionally provide --sdcard-adaptor numato to use the Numato layout.

Signed-off-by: Joel Stanley <joel@jms.id.au>

Collect --with-ethernet/--with-etherbone, --with-spi-sdcard/--with-sdcard,
etc. into ArgumentParser.add_mutually_exclusive_group()s.  That way, we
get pretty --help output, and appropriate error messages if somebody
tries to ask for something that doesn't make sense.

The SoC reset added recently creates a path between sys_clk and pll.clkin
clock domains that is reported by the tools but that can be safely ignored.

./arty.py --variant=a7-35 or a7-100
./arty_s7.py --variant=s7-50 or s7-25

Signed-off-by: Robert Winkler <rwinkler@antmicro.com>

targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.

Default to Chaser mode and similar user interface than GPIOOut.