rz_easyfpga: adjust SDRAM clk phase, also add 1:2 rate

- also add 1:2 rate

With colorbars for now, need to free up BRAMS for Video Terminal (or finish HyperRAM support).

sipeed_tang_nano: Add SPI Flash, Enable CPU and use new external SPI Flash support from OpenFPGALoader.

./sipeed_tang_nano_4k.py --cpu-type=vexriscv --cpu-variant=lite --build --flash

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2021 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Sep 17 2021 15:54:08
 BIOS CRC passed (6cc6de6d)

 Migen git sha1: a5bc262
 LiteX git sha1: 46cd9c5a

--=============== SoC ==================--
CPU:		VexRiscv_Lite @ 27MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		64KiB
SRAM:		8KiB
FLASH:		4096KiB

--========== Initialization ============--

Initializing W25Q32 SPI Flash @0x80000000...
SPI Flash clk configured to 13 MHz
Memspeed at 0x80000000 (Sequential, 4.0KiB)...
   Read speed: 1.3MiB/s
Memspeed at 0x80000000 (Random, 4.0KiB)...
   Read speed: 521.9KiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>

Update README.md

FPGA on "Zybo Z7" is a 7-Series Zynq not a Zynq Ultrascale+

Add runber support

platforms/sipeed_tang_nano_4k: fix period computation

Add Mojo V3 support

platforms/sipeed_tang_nano_4k: add P6 and P7 connectors

Add Alchitry Au as new board

./sispeed_tang_nano_4k.py --build --load

Build with Gowin EDA.
Load with OpenFPGALoader.

arty: Switch SPI Flash rate to 1:2 (DDR) (Possible on Arty since SPI Flash's clk does not require use of STARTUPE2).

On the Digilent Arty, the SPI Flash's clk is connected to CCLK (that can be driven
through the STARTUPE2) but also to another generic IO that can be use to drive the
clock through DDR primitives.