With the root hub unbinding in usb_stop(), there is no need to do
a Sandbox-specific reset operation. usb_emul_reset() is no longer
used anywhere, drop it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

With the root hub unbinding in usb_stop(), there is no need to do
a blk uclass specific unbind operation.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

At present we only do device_remove() during usb stop. The DM API
device_remove() only marks the device state as inactivated, but
still keeps its USB topology (eg: parent, children, etc) in the DM
device structure. There is no issue if we only start USB subsystem
once and never stop it. But a big issue occurs when we do 'usb stop'
and 'usb start' multiple times.

Strange things may be observed with current implementation, like:
- the enumeration may report only 1 mass storage device is detected,
  but the total number of USB devices is correct.
- USB keyboard does not work anymore after a bunch of 'usb reset'
  even if 'usb tree' shows it is correctly identified.
- read/write flash drive via 'fatload usb' may complain "Bad device"

In fact, every time when USB host controller starts the enumeration
process, it takes random time for each USB port to show up online,
hence each USB device may appear in a different order from previous
enumeration, and gets assigned to a totally different USB address.
As a result, we end up using a stale USB topology in the DM device
structure which still reflects the previous enumeration result, and
it may create an exact same DM device name like generic_bus_0_dev_7
that is already in the DM device structure. And since the DM device
structure is there, there is no device_bind() call to bind driver to
the device during current enumeration process, eventually creating
an inconsistent software representation of the hardware topology, a
non-working USB subsystem.

The fix is to clear the unused USB topology in the usb_stop(), by
calling device_unbind() on each controller's root hub device, and
the unbinding will unbind all of its children automatically.

For Sandbox, we need scan the device tree each time when we start
the USB stack, in order to re-create the emulated USB devices and
bind drivers for them before we actually do the driver probe.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

At present the usb hub emulator always reports its downstream port
speed as full speed. Actually it is high speed for sandbox-flash,
and low speed for sandbox-keyb. We can determine the device speed
by checking its device descriptor bcdUSB field, and do the proper
hub port status report based on that.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

This can be useful outside of the sandbox usb emulation uclass
driver. Expose it as a public API with a proper prefix (usb_emul_).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Current emulator select logic in usb_emul_find_devnum() is to test
the USB address. The USB address of the device being enumerated is
initialized to zero at the beginning of the enumeration process in
usb_setup_device(). At this point, the saved USB address in the
platform data has not been assigned to any valid USB address either.
This means: the logic will select an emulator device according to
its sequence of declaring order in the device tree. Take test.dts
for example, flash-stick@0 will be selected before flash-stick@1.
But unfortunately such logic is wrong.

In fact USB devices show up in a random order during the enumeration
which means usb_emul_find_devnum() may be called on port 3 for keyb@3
before on port 0 for flash-stick@0.

To fix this, we introduce a new emulator uclass specific platdata
to store the USB device's port number on its parent hub, and update
the logic to test the port number instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

At present 'usb tree' shows that the root hub on the Sandbox USB
controller is at full speed. But its device descriptor says it's
USB 2.0, so let's report it as a high speed device.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

There is no such a parameter called 'bus'.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

This parameter is never used.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

During using dwc2 usb gadget, if usb message size is too small,
following cache misaligned warning is shown:

   CACHE: Misaligned operation at range [bfdbcb00, bfdbcb04]

Align size of invalidating dcache before starting DMA to remove the
warning.

Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>

The choice of "USB keyboard polling" cannot be optional as without
one mechanism being set, it just doesn't work. Set the default one
to CONFIG_SYS_USB_EVENT_POLL.

Fixes: ecad7051 ("configs: Migrate all of the existing USB symbols, except fastboot")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Update the generic EHCI driver to support a live tree.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Update the DWC2 USB driver to support a live tree.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Update the Rockchip xhci wrapper driver to support a live device tree.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

When EHCD and xHCD are enabled at the same time, USB storage device
driver will fail to read/write from/to the storage device attached
to the xHCI interface, due to its transfer blocks exceeds the xHCD
driver limitation.

With driver model, we have an API to get the controller's maximum
transfer size and we can use that to determine the storage driver's
capability of read/write.

Note: the non-DM version driver is still broken with xHCD and the
intent here is not to fix the non-DM one, since the xHCD itself is
already broken in places like 3.0 hub support, etc.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

This adds a new memeber max_xfer_blk in struct us_data to record
the maximum number of transfer blocks for the storage device.

It is set per HCD setting, and so far is to 65535 for EHCD and 20
for everything else.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

EHCD can handle any transfer length as long as there is enough free
heap space left, hence set the theoretical max number SIZE_MAX.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

xHCD allocates one segment which includes 64 TRBs for each endpoint
and the last TRB in this segment is configured as a link TRB to form
a TRB ring. Each TRB can transfer up to 64K bytes, however data
buffers referenced by transfer TRBs shall not span 64KB boundaries.
Hence the maximum number of TRBs we can use in one transfer is 62.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

The HCD may have limitation on the maximum bytes to be transferred
in a USB transfer. USB class driver needs to be aware of this.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

The Linux kernel driver sets the number of event segments and entries
to 1 , while the initial import of the xhci code set that values to 3
for reasons unknown. While most controllers are fine with more event
segments with more entries, there are standard-conformant controllers
(ie. Renesas RCar xHCI) which only support 1 event segment.

Set the number of event segments and event entries back to 1 to allow
such controllers to work with U-Boot xHCI stack. Note that the Renesas
controller correctly indicates ERST Max = 1 in HCSPARAMS2[7:4] .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>

memset(newpart, '\0', sizeof(newpart));
only initializes the firest 4 or 8 bytes of *newpart and not the whole
structure disk_part.

We should use sizeof(struct disk_part).

Instead of malloc and memset we can use calloc.

Identified by cppcheck.

Fixes: 09a49930 GPT: read partition table from device into a data structure
Reported-by: Coverity (CID: 167228)
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

The status register is optional in the AMD command sets, but it's
presence can be checked by reading out CFI table entry 0xc bit 0.
If the register is present, prefer using it's bit 7 to determine
if the flash is busy over reading the flash ; this is needed ie.
on Hyperflash memories.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>

Embed the flash base into struct flash_info instead of having ad-hoc
static array in the code. This does not only remove static variable,
but also allows CFI-like controllers, ie. HyperFlash ones, to use most
of the CFI flash code by populating the flash_info with matching base
address.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>

The ClearFog Base boot from UART when setting the DIP switches to 01001.
Unfortunately, the SPL code sometimes fails to detect the UART boot
method at run-time. Add an alternative SAR UART boot value to fix this.

Note that this alternative value is not documented (Armada 38x Hardware
Specifications, Table 48). But experimentations showed it on the
ClearFog Base.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>

dram_ecc_scrubbing() had code to skip unused DRAM banks but it would not
work because mvebu_sdram_bs() returns 0 and the code was subtracting 1
before checking the size. Remove the -1 from the bank size and the +1
from the total which will skip unused banks and still calculate the
correct size. Put the -1 where it is needed for scrubbing via the xor
engine.

Reported-by: Joshua Scott <joshua.scott@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>

The Armada-38x has 1.8GHz and 2.0GHz variants. Add entries for these
variants to the sar_freq_tab.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>

Display more information about the current RAM configuration. With these
changes the output on a 88F6820 board is

  SoC:   MV88F6820-A0 at 1600 MHz
  DRAM:  2 GiB (800 MHz, 32-bit, ECC not enabled)

Signed-off-by: Joshua Scott <joshua.scott@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>

These SoCs are network packet processors (switch chips) with integrated
ARMv7 cores. They share a great deal of commonality with the Armada-XP
CPUs.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>

Currently, we support 2 "theadorable" MVEBU build targets. One with a
stripped down configuration (theadorable) and one with a full blown
configuration (theadorable_debug), including PCI, ethernet etc. When
we introduced these configs, the plan was to remove the debug version
at some point. But now it seems better to keep the full-blown version
and remove the "non-debug" version instead.

At a later stage, I will rename the remaining "theadorable_debug"
target into a more fitting one.

Signed-off-by: Stefan Roese <sr@denx.de>

This converts the following to Kconfig:
   CONFIG_MVNETA

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>

In some of the QSPI controller version, there must be atleast
128bit data available in TX FIFO for any pop operation otherwise
error bit will be set. The code will not make any behavior change
for previous controller as the transfer data size in ipcr register
is still the same.

Patch is tested on LS1046A which do not require 16 bytes aligned and
LS1088A which require 16 bytes aligned data in TX FIFO

Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Anupam Kumar <anupam.kumar_1@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>

Spansion S25FS256S and S25FL256S flashes have equal JEDEC ID and ext ID.
As far as S25FL256S occures in spi_flash_ids before S25FS256S, U-Boot
incorrectly detects FS flash as FL. Thus its better to compare with
S25FS256S first.

Signed-off-by: Vsevolod Gribov <vgribov@larch-networks.com>
[Added S-o-b]
Signed-off-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>

The flash chip is 2 MiB , organized as 32 x 64 kiB sectors .
Rectify the entry to match the datasheet, reality and Linux SNOR IDs.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>

Add MT35XU512ABA1G12 parameters to NOR flash parameters array.

The MT35XU512ABA1G12 only supports 1 bit mode and 8 bits. It can't support
dual and quad. Supports subsector erase with 4KB granularity, have support
of FSR(flag status register) and flash size is 64MB.

Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>