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uint32_t ctrl;
uint16_t data = 0;
uint8_t i;
/* In order to read a register from the PHY, we need to shift in a total
* of 18 bits from the PHY. The first two bit (turnaround) times are used
* to avoid contention on the MDIO pin when a read operation is performed.
* These two bits are ignored by us and thrown away. Bits are "shifted in"
* by raising the input to the Management Data Clock (setting the MDC bit),
* and then reading the value of the MDIO bit.
*/
ctrl = E1000_READ_REG(hw, CTRL);
/* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
ctrl &= ~E1000_CTRL_MDIO_DIR;
ctrl &= ~E1000_CTRL_MDIO;
E1000_WRITE_REG(hw, CTRL, ctrl);
E1000_WRITE_FLUSH(hw);
/* Raise and Lower the clock before reading in the data. This accounts for
* the turnaround bits. The first clock occurred when we clocked out the
* last bit of the Register Address.
*/
e1000_raise_mdi_clk(hw, &ctrl);
e1000_lower_mdi_clk(hw, &ctrl);
for (data = 0, i = 0; i < 16; i++) {
data = data << 1;
e1000_raise_mdi_clk(hw, &ctrl);
ctrl = E1000_READ_REG(hw, CTRL);
/* Check to see if we shifted in a "1". */
if (ctrl & E1000_CTRL_MDIO)
data |= 1;
e1000_lower_mdi_clk(hw, &ctrl);
}
e1000_raise_mdi_clk(hw, &ctrl);
e1000_lower_mdi_clk(hw, &ctrl);
return data;
}
/*****************************************************************************
* Reads the value from a PHY register
*
* hw - Struct containing variables accessed by shared code
* reg_addr - address of the PHY register to read
******************************************************************************/
static int
e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
{
uint32_t i;
uint32_t mdic = 0;
const uint32_t phy_addr = 1;
if (reg_addr > MAX_PHY_REG_ADDRESS) {
DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
return -E1000_ERR_PARAM;
}
if (hw->mac_type > e1000_82543) {
/* Set up Op-code, Phy Address, and register address in the MDI
* Control register. The MAC will take care of interfacing with the
* PHY to retrieve the desired data.
*/
mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
(phy_addr << E1000_MDIC_PHY_SHIFT) |
(E1000_MDIC_OP_READ));
E1000_WRITE_REG(hw, MDIC, mdic);
/* Poll the ready bit to see if the MDI read completed */
for (i = 0; i < 64; i++) {
udelay(10);
mdic = E1000_READ_REG(hw, MDIC);
if (mdic & E1000_MDIC_READY)
break;
}
if (!(mdic & E1000_MDIC_READY)) {
DEBUGOUT("MDI Read did not complete\n");
return -E1000_ERR_PHY;
}
if (mdic & E1000_MDIC_ERROR) {
DEBUGOUT("MDI Error\n");
return -E1000_ERR_PHY;
}
*phy_data = (uint16_t) mdic;
} else {
/* We must first send a preamble through the MDIO pin to signal the
* beginning of an MII instruction. This is done by sending 32
* consecutive "1" bits.
*/
e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
/* Now combine the next few fields that are required for a read
* operation. We use this method instead of calling the
* e1000_shift_out_mdi_bits routine five different times. The format of
* a MII read instruction consists of a shift out of 14 bits and is
* defined as follows:
* <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
* followed by a shift in of 18 bits. This first two bits shifted in
* are TurnAround bits used to avoid contention on the MDIO pin when a
* READ operation is performed. These two bits are thrown away
* followed by a shift in of 16 bits which contains the desired data.
*/
mdic = ((reg_addr) | (phy_addr << 5) |
(PHY_OP_READ << 10) | (PHY_SOF << 12));
e1000_shift_out_mdi_bits(hw, mdic, 14);
/* Now that we've shifted out the read command to the MII, we need to
* "shift in" the 16-bit value (18 total bits) of the requested PHY
* register address.
*/
*phy_data = e1000_shift_in_mdi_bits(hw);
}
return 0;
}
/******************************************************************************
* Writes a value to a PHY register
*
* hw - Struct containing variables accessed by shared code
* reg_addr - address of the PHY register to write
* data - data to write to the PHY
******************************************************************************/
static int
e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
{
uint32_t i;
uint32_t mdic = 0;
const uint32_t phy_addr = 1;
if (reg_addr > MAX_PHY_REG_ADDRESS) {
DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
return -E1000_ERR_PARAM;
}
if (hw->mac_type > e1000_82543) {
/* Set up Op-code, Phy Address, register address, and data intended
* for the PHY register in the MDI Control register. The MAC will take
* care of interfacing with the PHY to send the desired data.
*/
mdic = (((uint32_t) phy_data) |
(reg_addr << E1000_MDIC_REG_SHIFT) |
(phy_addr << E1000_MDIC_PHY_SHIFT) |
(E1000_MDIC_OP_WRITE));
E1000_WRITE_REG(hw, MDIC, mdic);
/* Poll the ready bit to see if the MDI read completed */
for (i = 0; i < 64; i++) {
udelay(10);
mdic = E1000_READ_REG(hw, MDIC);
if (mdic & E1000_MDIC_READY)
break;
}
if (!(mdic & E1000_MDIC_READY)) {
DEBUGOUT("MDI Write did not complete\n");
return -E1000_ERR_PHY;
}
} else {
/* We'll need to use the SW defined pins to shift the write command
* out to the PHY. We first send a preamble to the PHY to signal the
* beginning of the MII instruction. This is done by sending 32
* consecutive "1" bits.
*/
e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
/* Now combine the remaining required fields that will indicate a
* write operation. We use this method instead of calling the
* e1000_shift_out_mdi_bits routine for each field in the command. The
* format of a MII write instruction is as follows:
* <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
*/
mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
(PHY_OP_WRITE << 12) | (PHY_SOF << 14));
mdic <<= 16;
mdic |= (uint32_t) phy_data;
e1000_shift_out_mdi_bits(hw, mdic, 32);
}
return 0;
}
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/******************************************************************************
* Checks if PHY reset is blocked due to SOL/IDER session, for example.
* Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
* the caller to figure out how to deal with it.
*
* hw - Struct containing variables accessed by shared code
*
* returns: - E1000_BLK_PHY_RESET
* E1000_SUCCESS
*
*****************************************************************************/
int32_t
e1000_check_phy_reset_block(struct e1000_hw *hw)
{
uint32_t manc = 0;
uint32_t fwsm = 0;
if (hw->mac_type == e1000_ich8lan) {
fwsm = E1000_READ_REG(hw, FWSM);
return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
: E1000_BLK_PHY_RESET;
}
if (hw->mac_type > e1000_82547_rev_2)
manc = E1000_READ_REG(hw, MANC);
return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
E1000_BLK_PHY_RESET : E1000_SUCCESS;
}
/***************************************************************************
* Checks if the PHY configuration is done
*
* hw: Struct containing variables accessed by shared code
*
* returns: - E1000_ERR_RESET if fail to reset MAC
* E1000_SUCCESS at any other case.
*
***************************************************************************/
static int32_t
e1000_get_phy_cfg_done(struct e1000_hw *hw)
{
int32_t timeout = PHY_CFG_TIMEOUT;
uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
DEBUGFUNC();
switch (hw->mac_type) {
default:
mdelay(10);
break;
case e1000_80003es2lan:
/* Separate *_CFG_DONE_* bit for each port */
if (e1000_is_second_port(hw))
/* Fall Through */
case e1000_82571:
case e1000_82572:
while (timeout) {
if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
break;
else
mdelay(1);
timeout--;
}
if (!timeout) {
DEBUGOUT("MNG configuration cycle has not "
"completed.\n");
return -E1000_ERR_RESET;
}
break;
}
return E1000_SUCCESS;
}
/******************************************************************************
* Returns the PHY to the power-on reset state
*
* hw - Struct containing variables accessed by shared code
******************************************************************************/
e1000_phy_hw_reset(struct e1000_hw *hw)
{
uint16_t swfw = E1000_SWFW_PHY0_SM;
uint32_t ctrl, ctrl_ext;
uint32_t led_ctrl;
int32_t ret_val;
/* In the case of the phy reset being blocked, it's not an error, we
* simply return success without performing the reset. */
ret_val = e1000_check_phy_reset_block(hw);
if (ret_val)
return E1000_SUCCESS;
DEBUGOUT("Resetting Phy...\n");
if (hw->mac_type > e1000_82543) {
if (e1000_is_second_port(hw))
if (e1000_swfw_sync_acquire(hw, swfw)) {
DEBUGOUT("Unable to acquire swfw sync\n");
return -E1000_ERR_SWFW_SYNC;
}
/* Read the device control register and assert the E1000_CTRL_PHY_RST
* bit. Then, take it out of reset.
*/
ctrl = E1000_READ_REG(hw, CTRL);
E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
E1000_WRITE_FLUSH(hw);
if (hw->mac_type < e1000_82571)
udelay(10);
else
udelay(100);
E1000_WRITE_REG(hw, CTRL, ctrl);
E1000_WRITE_FLUSH(hw);
if (hw->mac_type >= e1000_82571)
mdelay(10);
} else {
/* Read the Extended Device Control Register, assert the PHY_RESET_DIR
* bit to put the PHY into reset. Then, take it out of reset.
*/
ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
E1000_WRITE_FLUSH(hw);
mdelay(10);
ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
E1000_WRITE_FLUSH(hw);
}
udelay(150);
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if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
/* Configure activity LED after PHY reset */
led_ctrl = E1000_READ_REG(hw, LEDCTL);
led_ctrl &= IGP_ACTIVITY_LED_MASK;
led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
}
/* Wait for FW to finish PHY configuration. */
ret_val = e1000_get_phy_cfg_done(hw);
if (ret_val != E1000_SUCCESS)
return ret_val;
return ret_val;
}
/******************************************************************************
* IGP phy init script - initializes the GbE PHY
*
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
static void
e1000_phy_init_script(struct e1000_hw *hw)
{
uint32_t ret_val;
uint16_t phy_saved_data;
DEBUGFUNC();
if (hw->phy_init_script) {
mdelay(20);
/* Save off the current value of register 0x2F5B to be
* restored at the end of this routine. */
ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
/* Disabled the PHY transmitter */
e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
mdelay(20);
e1000_write_phy_reg(hw, 0x0000, 0x0140);
mdelay(5);
switch (hw->mac_type) {
case e1000_82541:
case e1000_82547:
e1000_write_phy_reg(hw, 0x1F95, 0x0001);
e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
e1000_write_phy_reg(hw, 0x1F79, 0x0018);
e1000_write_phy_reg(hw, 0x1F30, 0x1600);
e1000_write_phy_reg(hw, 0x1F31, 0x0014);
e1000_write_phy_reg(hw, 0x1F32, 0x161C);
e1000_write_phy_reg(hw, 0x1F94, 0x0003);
e1000_write_phy_reg(hw, 0x1F96, 0x003F);
e1000_write_phy_reg(hw, 0x2010, 0x0008);
break;
case e1000_82541_rev_2:
case e1000_82547_rev_2:
e1000_write_phy_reg(hw, 0x1F73, 0x0099);
break;
default:
break;
}
e1000_write_phy_reg(hw, 0x0000, 0x3300);
mdelay(20);
/* Now enable the transmitter */
if (!ret_val)
e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
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if (hw->mac_type == e1000_82547) {
uint16_t fused, fine, coarse;
/* Move to analog registers page */
e1000_read_phy_reg(hw,
IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
e1000_read_phy_reg(hw,
IGP01E1000_ANALOG_FUSE_STATUS, &fused);
fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
coarse = fused
& IGP01E1000_ANALOG_FUSE_COARSE_MASK;
if (coarse >
IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
coarse -=
IGP01E1000_ANALOG_FUSE_COARSE_10;
fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
} else if (coarse
== IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
fused = (fused
& IGP01E1000_ANALOG_FUSE_POLY_MASK) |
(fine
& IGP01E1000_ANALOG_FUSE_FINE_MASK) |
(coarse
& IGP01E1000_ANALOG_FUSE_COARSE_MASK);
e1000_write_phy_reg(hw,
IGP01E1000_ANALOG_FUSE_CONTROL, fused);
e1000_write_phy_reg(hw,
IGP01E1000_ANALOG_FUSE_BYPASS,
IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
}
}
}
}
/******************************************************************************
* Resets the PHY
*
* hw - Struct containing variables accessed by shared code
*
******************************************************************************/
e1000_phy_reset(struct e1000_hw *hw)
{
uint16_t phy_data;
DEBUGFUNC();
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/* In the case of the phy reset being blocked, it's not an error, we
* simply return success without performing the reset. */
ret_val = e1000_check_phy_reset_block(hw);
if (ret_val)
return E1000_SUCCESS;
switch (hw->phy_type) {
case e1000_phy_igp:
case e1000_phy_igp_2:
case e1000_phy_igp_3:
case e1000_phy_ife:
ret_val = e1000_phy_hw_reset(hw);
if (ret_val)
return ret_val;
break;
default:
ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
if (ret_val)
return ret_val;
phy_data |= MII_CR_RESET;
ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
if (ret_val)
return ret_val;
udelay(1);
break;
if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
e1000_phy_init_script(hw);
return E1000_SUCCESS;
static int e1000_set_phy_type (struct e1000_hw *hw)
DEBUGFUNC ();
if (hw->mac_type == e1000_undefined)
return -E1000_ERR_PHY_TYPE;
switch (hw->phy_id) {
case M88E1000_E_PHY_ID:
case M88E1000_I_PHY_ID:
case M88E1011_I_PHY_ID:
hw->phy_type = e1000_phy_m88;
break;
case IGP01E1000_I_PHY_ID:
if (hw->mac_type == e1000_82541 ||
hw->mac_type == e1000_82541_rev_2 ||
hw->mac_type == e1000_82547 ||
hw->mac_type == e1000_82547_rev_2) {
hw->phy_type = e1000_phy_igp;
break;
}
case IGP03E1000_E_PHY_ID:
hw->phy_type = e1000_phy_igp_3;
break;
case IFE_E_PHY_ID:
case IFE_PLUS_E_PHY_ID:
case IFE_C_E_PHY_ID:
hw->phy_type = e1000_phy_ife;
break;
case GG82563_E_PHY_ID:
if (hw->mac_type == e1000_80003es2lan) {
hw->phy_type = e1000_phy_gg82563;
case BME1000_E_PHY_ID:
hw->phy_type = e1000_phy_bm;
break;
/* Fall Through */
default:
/* Should never have loaded on this device */
hw->phy_type = e1000_phy_undefined;
return -E1000_ERR_PHY_TYPE;
}
return E1000_SUCCESS;
/******************************************************************************
* Probes the expected PHY address for known PHY IDs
*
* hw - Struct containing variables accessed by shared code
******************************************************************************/
e1000_detect_gig_phy(struct e1000_hw *hw)
{
uint16_t phy_id_high, phy_id_low;
/* The 82571 firmware may still be configuring the PHY. In this
* case, we cannot access the PHY until the configuration is done. So
* we explicitly set the PHY values. */
if (hw->mac_type == e1000_82571 ||
hw->mac_type == e1000_82572) {
hw->phy_id = IGP01E1000_I_PHY_ID;
hw->phy_type = e1000_phy_igp_2;
return E1000_SUCCESS;
/* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
* work- around that forces PHY page 0 to be set or the reads fail.
* The rest of the code in this routine uses e1000_read_phy_reg to
* read the PHY ID. So for ESB-2 we need to have this set so our
* reads won't fail. If the attached PHY is not a e1000_phy_gg82563,
* the routines below will figure this out as well. */
if (hw->mac_type == e1000_80003es2lan)
hw->phy_type = e1000_phy_gg82563;
/* Read the PHY ID Registers to identify which PHY is onboard. */
ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
if (ret_val)
return ret_val;
hw->phy_id = (uint32_t) (phy_id_high << 16);
udelay(20);
ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
if (ret_val)
return ret_val;
hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
switch (hw->mac_type) {
case e1000_82543:
if (hw->phy_id == M88E1000_E_PHY_ID)
match = TRUE;
break;
case e1000_82544:
if (hw->phy_id == M88E1000_I_PHY_ID)
match = TRUE;
break;
case e1000_82540:
case e1000_82545:
if (hw->phy_id == M88E1011_I_PHY_ID)
match = TRUE;
break;
case e1000_82547:
case e1000_82547_rev_2:
if(hw->phy_id == IGP01E1000_I_PHY_ID)
match = TRUE;
break;
case e1000_82573:
if (hw->phy_id == M88E1111_I_PHY_ID)
match = TRUE;
break;
case e1000_82574:
if (hw->phy_id == BME1000_E_PHY_ID)
match = TRUE;
break;
case e1000_80003es2lan:
if (hw->phy_id == GG82563_E_PHY_ID)
match = TRUE;
break;
case e1000_ich8lan:
if (hw->phy_id == IGP03E1000_E_PHY_ID)
match = TRUE;
if (hw->phy_id == IFE_E_PHY_ID)
match = TRUE;
if (hw->phy_id == IFE_PLUS_E_PHY_ID)
match = TRUE;
if (hw->phy_id == IFE_C_E_PHY_ID)
match = TRUE;
break;
default:
DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
return -E1000_ERR_CONFIG;
}
phy_init_status = e1000_set_phy_type(hw);
if ((match) && (phy_init_status == E1000_SUCCESS)) {
DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
return 0;
}
DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
return -E1000_ERR_PHY;
}
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/*****************************************************************************
* Set media type and TBI compatibility.
*
* hw - Struct containing variables accessed by shared code
* **************************************************************************/
void
e1000_set_media_type(struct e1000_hw *hw)
{
uint32_t status;
DEBUGFUNC();
if (hw->mac_type != e1000_82543) {
/* tbi_compatibility is only valid on 82543 */
hw->tbi_compatibility_en = FALSE;
}
switch (hw->device_id) {
case E1000_DEV_ID_82545GM_SERDES:
case E1000_DEV_ID_82546GB_SERDES:
case E1000_DEV_ID_82571EB_SERDES:
case E1000_DEV_ID_82571EB_SERDES_DUAL:
case E1000_DEV_ID_82571EB_SERDES_QUAD:
case E1000_DEV_ID_82572EI_SERDES:
case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
hw->media_type = e1000_media_type_internal_serdes;
break;
default:
switch (hw->mac_type) {
case e1000_82542_rev2_0:
case e1000_82542_rev2_1:
hw->media_type = e1000_media_type_fiber;
break;
case e1000_ich8lan:
case e1000_82573:
/* The STATUS_TBIMODE bit is reserved or reused
* for the this device.
*/
hw->media_type = e1000_media_type_copper;
break;
default:
status = E1000_READ_REG(hw, STATUS);
if (status & E1000_STATUS_TBIMODE) {
hw->media_type = e1000_media_type_fiber;
/* tbi_compatibility not valid on fiber */
hw->tbi_compatibility_en = FALSE;
} else {
hw->media_type = e1000_media_type_copper;
}
break;
}
}
}
/**
* e1000_sw_init - Initialize general software structures (struct e1000_adapter)
*
* e1000_sw_init initializes the Adapter private data structure.
* Fields are initialized based on PCI device information and
* OS network device settings (MTU size).
**/
static int
e1000_sw_init(struct eth_device *nic)
{
struct e1000_hw *hw = (typeof(hw)) nic->priv;
int result;
/* PCI config space info */
pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
&hw->subsystem_vendor_id);
pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
/* identify the MAC */
result = e1000_set_mac_type(hw);
if (result) {
E1000_ERR(hw->nic, "Unknown MAC Type\n");
switch (hw->mac_type) {
default:
break;
case e1000_82541:
case e1000_82547:
case e1000_82541_rev_2:
case e1000_82547_rev_2:
hw->phy_init_script = 1;
break;
}
/* flow control settings */
hw->fc_high_water = E1000_FC_HIGH_THRESH;
hw->fc_low_water = E1000_FC_LOW_THRESH;
hw->fc_pause_time = E1000_FC_PAUSE_TIME;
hw->fc_send_xon = 1;
/* Media type - copper or fiber */
if (hw->mac_type >= e1000_82543) {
uint32_t status = E1000_READ_REG(hw, STATUS);
if (status & E1000_STATUS_TBIMODE) {
DEBUGOUT("fiber interface\n");
hw->media_type = e1000_media_type_fiber;
} else {
DEBUGOUT("copper interface\n");
hw->media_type = e1000_media_type_copper;
}
} else {
hw->media_type = e1000_media_type_fiber;
}
hw->tbi_compatibility_en = TRUE;
hw->wait_autoneg_complete = TRUE;
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if (hw->mac_type < e1000_82543)
hw->report_tx_early = 0;
else
hw->report_tx_early = 1;
return E1000_SUCCESS;
}
void
fill_rx(struct e1000_hw *hw)
{
struct e1000_rx_desc *rd;
rx_last = rx_tail;
rd = rx_base + rx_tail;
rx_tail = (rx_tail + 1) % 8;
memset(rd, 0, 16);
rd->buffer_addr = cpu_to_le64((u32) & packet);
E1000_WRITE_REG(hw, RDT, rx_tail);
}
/**
* e1000_configure_tx - Configure 8254x Transmit Unit after Reset
* @adapter: board private structure
*
* Configure the Tx unit of the MAC after a reset.
**/
static void
e1000_configure_tx(struct e1000_hw *hw)
{
unsigned long ptr;
unsigned long tctl;
unsigned long tipg, tarc;
uint32_t ipgr1, ipgr2;
ptr = (u32) tx_pool;
if (ptr & 0xf)
ptr = (ptr + 0x10) & (~0xf);
tx_base = (typeof(tx_base)) ptr;
E1000_WRITE_REG(hw, TDBAL, (u32) tx_base);
E1000_WRITE_REG(hw, TDBAH, 0);
E1000_WRITE_REG(hw, TDLEN, 128);
/* Setup the HW Tx Head and Tail descriptor pointers */
E1000_WRITE_REG(hw, TDH, 0);
E1000_WRITE_REG(hw, TDT, 0);
tx_tail = 0;
/* Set the default values for the Tx Inter Packet Gap timer */
if (hw->mac_type <= e1000_82547_rev_2 &&
(hw->media_type == e1000_media_type_fiber ||
hw->media_type == e1000_media_type_internal_serdes))
tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
else
tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
/* Set the default values for the Tx Inter Packet Gap timer */
switch (hw->mac_type) {
case e1000_82542_rev2_0:
case e1000_82542_rev2_1:
tipg = DEFAULT_82542_TIPG_IPGT;
ipgr1 = DEFAULT_82542_TIPG_IPGR1;
ipgr2 = DEFAULT_82542_TIPG_IPGR2;
break;
case e1000_80003es2lan:
ipgr1 = DEFAULT_82543_TIPG_IPGR1;
ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
ipgr1 = DEFAULT_82543_TIPG_IPGR1;
ipgr2 = DEFAULT_82543_TIPG_IPGR2;
break;
tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
E1000_WRITE_REG(hw, TIPG, tipg);
/* Program the Transmit Control Register */
tctl = E1000_READ_REG(hw, TCTL);
tctl &= ~E1000_TCTL_CT;
tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
(E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
tarc = E1000_READ_REG(hw, TARC0);
/* set the speed mode bit, we'll clear it if we're not at
* gigabit link later */
/* git bit can be set to 1*/
} else if (hw->mac_type == e1000_80003es2lan) {
tarc = E1000_READ_REG(hw, TARC0);
tarc |= 1;
E1000_WRITE_REG(hw, TARC0, tarc);
tarc = E1000_READ_REG(hw, TARC1);
tarc |= 1;
E1000_WRITE_REG(hw, TARC1, tarc);
}
e1000_config_collision_dist(hw);
/* Setup Transmit Descriptor Settings for eop descriptor */
hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
/* Need to set up RS bit */
if (hw->mac_type < e1000_82543)
hw->txd_cmd |= E1000_TXD_CMD_RPS;
hw->txd_cmd |= E1000_TXD_CMD_RS;
E1000_WRITE_REG(hw, TCTL, tctl);
}
/**
* e1000_setup_rctl - configure the receive control register
* @adapter: Board private structure
**/
static void
e1000_setup_rctl(struct e1000_hw *hw)
{
uint32_t rctl;
rctl = E1000_READ_REG(hw, RCTL);
rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
| E1000_RCTL_RDMTS_HALF; /* |
(hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
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if (hw->tbi_compatibility_on == 1)
rctl |= E1000_RCTL_SBP;
else
rctl &= ~E1000_RCTL_SBP;
rctl &= ~(E1000_RCTL_SZ_4096);
rctl |= E1000_RCTL_SZ_2048;
rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
E1000_WRITE_REG(hw, RCTL, rctl);
}
/**
* e1000_configure_rx - Configure 8254x Receive Unit after Reset
* @adapter: board private structure
*
* Configure the Rx unit of the MAC after a reset.
**/
static void
e1000_configure_rx(struct e1000_hw *hw)
{
unsigned long ptr;
rx_tail = 0;
/* make sure receives are disabled while setting up the descriptors */
rctl = E1000_READ_REG(hw, RCTL);
E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
if (hw->mac_type >= e1000_82540) {
/* Set the interrupt throttling rate. Value is calculated
* as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
#define MAX_INTS_PER_SEC 8000
#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
}
if (hw->mac_type >= e1000_82571) {
ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
/* Reset delay timers after every interrupt */
ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
E1000_WRITE_FLUSH(hw);
}
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/* Setup the Base and Length of the Rx Descriptor Ring */
ptr = (u32) rx_pool;
if (ptr & 0xf)
ptr = (ptr + 0x10) & (~0xf);
rx_base = (typeof(rx_base)) ptr;
E1000_WRITE_REG(hw, RDBAL, (u32) rx_base);
E1000_WRITE_REG(hw, RDBAH, 0);
E1000_WRITE_REG(hw, RDLEN, 128);
/* Setup the HW Rx Head and Tail Descriptor Pointers */
E1000_WRITE_REG(hw, RDH, 0);
E1000_WRITE_REG(hw, RDT, 0);
/* Enable Receives */
E1000_WRITE_REG(hw, RCTL, rctl);
fill_rx(hw);
}
/**************************************************************************
POLL - Wait for a frame
***************************************************************************/
static int
e1000_poll(struct eth_device *nic)
{
struct e1000_hw *hw = nic->priv;
struct e1000_rx_desc *rd;
/* return true if there's an ethernet packet ready to read */
rd = rx_base + rx_last;
if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD)
return 0;
/*DEBUGOUT("recv: packet len=%d \n", rd->length); */
NetReceive((uchar *)packet, le32_to_cpu(rd->length));
fill_rx(hw);
return 1;
}
/**************************************************************************
TRANSMIT - Transmit a frame
***************************************************************************/
static int e1000_transmit(struct eth_device *nic, void *packet, int length)
void *nv_packet = (void *)packet;
struct e1000_hw *hw = nic->priv;
struct e1000_tx_desc *txp;
int i = 0;