Skip to content
Snippets Groups Projects
e1000.c 154 KiB
Newer Older
  • Learn to ignore specific revisions
  • 	if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
    		DEBUGOUT("Looking for Link\n");
    		for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
    			mdelay(10);
    			status = E1000_READ_REG(hw, STATUS);
    			if (status & E1000_STATUS_LU)
    				break;
    		}
    		if (i == (LINK_UP_TIMEOUT / 10)) {
    
    Wolfgang Denk's avatar
    Wolfgang Denk committed
    			/* AutoNeg failed to achieve a link, so we'll call
    
    			 * e1000_check_for_link. This routine will force the link up if we
    			 * detect a signal. This will allow us to communicate with
    			 * non-autonegotiating link partners.
    			 */
    			DEBUGOUT("Never got a valid link from auto-neg!!!\n");
    			hw->autoneg_failed = 1;
    			ret_val = e1000_check_for_link(nic);
    			if (ret_val < 0) {
    				DEBUGOUT("Error while checking for link\n");
    				return ret_val;
    			}
    			hw->autoneg_failed = 0;
    		} else {
    			hw->autoneg_failed = 0;
    			DEBUGOUT("Valid Link Found\n");
    		}
    
    2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346
    	} else {
    		DEBUGOUT("No Signal Detected\n");
    		return -E1000_ERR_NOLINK;
    	}
    	return 0;
    }
    
    /******************************************************************************
    * Make sure we have a valid PHY and change PHY mode before link setup.
    *
    * hw - Struct containing variables accessed by shared code
    ******************************************************************************/
    static int32_t
    e1000_copper_link_preconfig(struct e1000_hw *hw)
    {
    	uint32_t ctrl;
    	int32_t ret_val;
    	uint16_t phy_data;
    
    	DEBUGFUNC();
    
    	ctrl = E1000_READ_REG(hw, CTRL);
    	/* With 82543, we need to force speed and duplex on the MAC equal to what
    	 * the PHY speed and duplex configuration is. In addition, we need to
    	 * perform a hardware reset on the PHY to take it out of reset.
    	 */
    	if (hw->mac_type > e1000_82543) {
    		ctrl |= E1000_CTRL_SLU;
    		ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
    		E1000_WRITE_REG(hw, CTRL, ctrl);
    	} else {
    		ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
    				| E1000_CTRL_SLU);
    		E1000_WRITE_REG(hw, CTRL, ctrl);
    		ret_val = e1000_phy_hw_reset(hw);
    		if (ret_val)
    			return ret_val;
    	}
    
    	/* Make sure we have a valid PHY */
    	ret_val = e1000_detect_gig_phy(hw);
    	if (ret_val) {
    		DEBUGOUT("Error, did not detect valid phy.\n");
    		return ret_val;
    	}
    	DEBUGOUT("Phy ID = %x \n", hw->phy_id);
    
    	/* Set PHY to class A mode (if necessary) */
    	ret_val = e1000_set_phy_mode(hw);
    	if (ret_val)
    		return ret_val;
    	if ((hw->mac_type == e1000_82545_rev_3) ||
    		(hw->mac_type == e1000_82546_rev_3)) {
    		ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
    				&phy_data);
    		phy_data |= 0x00000008;
    		ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
    				phy_data);
    	}
    
    	if (hw->mac_type <= e1000_82543 ||
    		hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
    		hw->mac_type == e1000_82541_rev_2
    		|| hw->mac_type == e1000_82547_rev_2)
    			hw->phy_reset_disable = FALSE;
    
    	return E1000_SUCCESS;
    }
    
    /*****************************************************************************
     *
     * This function sets the lplu state according to the active flag.  When
     * activating lplu this function also disables smart speed and vise versa.
     * lplu will not be activated unless the device autonegotiation advertisment
     * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
     * hw: Struct containing variables accessed by shared code
     * active - true to enable lplu false to disable lplu.
     *
     * returns: - E1000_ERR_PHY if fail to read/write the PHY
     *            E1000_SUCCESS at any other case.
     *
     ****************************************************************************/
    
    static int32_t
    e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active)
    {
    	uint32_t phy_ctrl = 0;
    	int32_t ret_val;
    	uint16_t phy_data;
    	DEBUGFUNC();
    
    	if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
    	    && hw->phy_type != e1000_phy_igp_3)
    		return E1000_SUCCESS;
    
    	/* During driver activity LPLU should not be used or it will attain link
    	 * from the lowest speeds starting from 10Mbps. The capability is used
    	 * for Dx transitions and states */
    	if (hw->mac_type == e1000_82541_rev_2
    			|| hw->mac_type == e1000_82547_rev_2) {
    		ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
    				&phy_data);
    		if (ret_val)
    			return ret_val;
    	} else if (hw->mac_type == e1000_ich8lan) {
    		/* MAC writes into PHY register based on the state transition
    		 * and start auto-negotiation. SW driver can overwrite the
    		 * settings in CSR PHY power control E1000_PHY_CTRL register. */
    		phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
    	} else {
    		ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
    				&phy_data);
    		if (ret_val)
    			return ret_val;
    	}
    
    	if (!active) {
    		if (hw->mac_type == e1000_82541_rev_2 ||
    			hw->mac_type == e1000_82547_rev_2) {
    			phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
    			ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
    					phy_data);
    			if (ret_val)
    				return ret_val;
    		} else {
    			if (hw->mac_type == e1000_ich8lan) {
    				phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
    				E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
    			} else {
    				phy_data &= ~IGP02E1000_PM_D3_LPLU;
    				ret_val = e1000_write_phy_reg(hw,
    					IGP02E1000_PHY_POWER_MGMT, phy_data);
    				if (ret_val)
    					return ret_val;
    			}
    		}
    
    	/* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
    	 * Dx states where the power conservation is most important.  During
    	 * driver activity we should enable SmartSpeed, so performance is
    	 * maintained. */
    		if (hw->smart_speed == e1000_smart_speed_on) {
    			ret_val = e1000_read_phy_reg(hw,
    					IGP01E1000_PHY_PORT_CONFIG, &phy_data);
    			if (ret_val)
    				return ret_val;
    
    			phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
    			ret_val = e1000_write_phy_reg(hw,
    					IGP01E1000_PHY_PORT_CONFIG, phy_data);
    			if (ret_val)
    				return ret_val;
    		} else if (hw->smart_speed == e1000_smart_speed_off) {
    			ret_val = e1000_read_phy_reg(hw,
    					IGP01E1000_PHY_PORT_CONFIG, &phy_data);
    			if (ret_val)
    				return ret_val;
    
    			phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
    			ret_val = e1000_write_phy_reg(hw,
    					IGP01E1000_PHY_PORT_CONFIG, phy_data);
    			if (ret_val)
    				return ret_val;
    		}
    
    	} else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
    		|| (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
    		(hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
    
    		if (hw->mac_type == e1000_82541_rev_2 ||
    		    hw->mac_type == e1000_82547_rev_2) {
    			phy_data |= IGP01E1000_GMII_FLEX_SPD;
    			ret_val = e1000_write_phy_reg(hw,
    					IGP01E1000_GMII_FIFO, phy_data);
    			if (ret_val)
    				return ret_val;
    		} else {
    			if (hw->mac_type == e1000_ich8lan) {
    				phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
    				E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
    			} else {
    				phy_data |= IGP02E1000_PM_D3_LPLU;
    				ret_val = e1000_write_phy_reg(hw,
    					IGP02E1000_PHY_POWER_MGMT, phy_data);
    				if (ret_val)
    					return ret_val;
    			}
    		}
    
    		/* When LPLU is enabled we should disable SmartSpeed */
    		ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
    				&phy_data);
    		if (ret_val)
    			return ret_val;
    
    		phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
    		ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
    				phy_data);
    		if (ret_val)
    			return ret_val;
    	}
    	return E1000_SUCCESS;
    }
    
    /*****************************************************************************
     *
     * This function sets the lplu d0 state according to the active flag.  When
     * activating lplu this function also disables smart speed and vise versa.
     * lplu will not be activated unless the device autonegotiation advertisment
     * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
     * hw: Struct containing variables accessed by shared code
     * active - true to enable lplu false to disable lplu.
     *
     * returns: - E1000_ERR_PHY if fail to read/write the PHY
     *            E1000_SUCCESS at any other case.
     *
     ****************************************************************************/
    
    static int32_t
    e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active)
    {
    	uint32_t phy_ctrl = 0;
    	int32_t ret_val;
    	uint16_t phy_data;
    	DEBUGFUNC();
    
    	if (hw->mac_type <= e1000_82547_rev_2)
    		return E1000_SUCCESS;
    
    	if (hw->mac_type == e1000_ich8lan) {
    		phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
    	} else {
    		ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
    				&phy_data);
    		if (ret_val)
    			return ret_val;
    	}
    
    	if (!active) {
    		if (hw->mac_type == e1000_ich8lan) {
    			phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
    			E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
    		} else {
    			phy_data &= ~IGP02E1000_PM_D0_LPLU;
    			ret_val = e1000_write_phy_reg(hw,
    					IGP02E1000_PHY_POWER_MGMT, phy_data);
    			if (ret_val)
    				return ret_val;
    		}
    
    	/* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
    	 * Dx states where the power conservation is most important.  During
    	 * driver activity we should enable SmartSpeed, so performance is
    	 * maintained. */
    		if (hw->smart_speed == e1000_smart_speed_on) {
    			ret_val = e1000_read_phy_reg(hw,
    					IGP01E1000_PHY_PORT_CONFIG, &phy_data);
    			if (ret_val)
    				return ret_val;
    
    			phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
    			ret_val = e1000_write_phy_reg(hw,
    					IGP01E1000_PHY_PORT_CONFIG, phy_data);
    			if (ret_val)
    				return ret_val;
    		} else if (hw->smart_speed == e1000_smart_speed_off) {
    			ret_val = e1000_read_phy_reg(hw,
    					IGP01E1000_PHY_PORT_CONFIG, &phy_data);
    			if (ret_val)
    				return ret_val;
    
    			phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
    			ret_val = e1000_write_phy_reg(hw,
    					IGP01E1000_PHY_PORT_CONFIG, phy_data);
    			if (ret_val)
    				return ret_val;
    		}
    
    
    	} else {
    
    		if (hw->mac_type == e1000_ich8lan) {
    			phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
    			E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
    		} else {
    			phy_data |= IGP02E1000_PM_D0_LPLU;
    			ret_val = e1000_write_phy_reg(hw,
    					IGP02E1000_PHY_POWER_MGMT, phy_data);
    			if (ret_val)
    				return ret_val;
    		}
    
    		/* When LPLU is enabled we should disable SmartSpeed */
    		ret_val = e1000_read_phy_reg(hw,
    				IGP01E1000_PHY_PORT_CONFIG, &phy_data);
    		if (ret_val)
    			return ret_val;
    
    		phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
    		ret_val = e1000_write_phy_reg(hw,
    				IGP01E1000_PHY_PORT_CONFIG, phy_data);
    		if (ret_val)
    			return ret_val;
    
    	}
    	return E1000_SUCCESS;
    }
    
    /********************************************************************
    * Copper link setup for e1000_phy_igp series.
    *
    * hw - Struct containing variables accessed by shared code
    *********************************************************************/
    static int32_t
    e1000_copper_link_igp_setup(struct e1000_hw *hw)
    {
    	uint32_t led_ctrl;
    	int32_t ret_val;
    	uint16_t phy_data;
    
    
    	DEBUGFUNC();
    
    
    	if (hw->phy_reset_disable)
    		return E1000_SUCCESS;
    
    	ret_val = e1000_phy_reset(hw);
    	if (ret_val) {
    		DEBUGOUT("Error Resetting the PHY\n");
    		return ret_val;
    	}
    
    	/* Wait 15ms for MAC to configure PHY from eeprom settings */
    	mdelay(15);
    	if (hw->mac_type != e1000_ich8lan) {
    		/* Configure activity LED after PHY reset */
    		led_ctrl = E1000_READ_REG(hw, LEDCTL);
    		led_ctrl &= IGP_ACTIVITY_LED_MASK;
    		led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
    		E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
    	}
    
    	/* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
    	if (hw->phy_type == e1000_phy_igp) {
    		/* disable lplu d3 during driver init */
    		ret_val = e1000_set_d3_lplu_state(hw, FALSE);
    		if (ret_val) {
    			DEBUGOUT("Error Disabling LPLU D3\n");
    			return ret_val;
    		}
    	}
    
    	/* disable lplu d0 during driver init */
    	ret_val = e1000_set_d0_lplu_state(hw, FALSE);
    	if (ret_val) {
    		DEBUGOUT("Error Disabling LPLU D0\n");
    		return ret_val;
    	}
    	/* Configure mdi-mdix settings */
    	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
    	if (ret_val)
    		return ret_val;
    
    	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
    		hw->dsp_config_state = e1000_dsp_config_disabled;
    		/* Force MDI for earlier revs of the IGP PHY */
    		phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
    				| IGP01E1000_PSCR_FORCE_MDI_MDIX);
    		hw->mdix = 1;
    
    	} else {
    		hw->dsp_config_state = e1000_dsp_config_enabled;
    		phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
    
    		switch (hw->mdix) {
    		case 1:
    			phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
    			break;
    		case 2:
    			phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
    			break;
    		case 0:
    		default:
    			phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
    			break;
    		}
    	}
    	ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
    	if (ret_val)
    		return ret_val;
    
    	/* set auto-master slave resolution settings */
    	if (hw->autoneg) {
    		e1000_ms_type phy_ms_setting = hw->master_slave;
    
    		if (hw->ffe_config_state == e1000_ffe_config_active)
    			hw->ffe_config_state = e1000_ffe_config_enabled;
    
    		if (hw->dsp_config_state == e1000_dsp_config_activated)
    			hw->dsp_config_state = e1000_dsp_config_enabled;
    
    		/* when autonegotiation advertisment is only 1000Mbps then we
    		  * should disable SmartSpeed and enable Auto MasterSlave
    		  * resolution as hardware default. */
    		if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
    			/* Disable SmartSpeed */
    			ret_val = e1000_read_phy_reg(hw,
    					IGP01E1000_PHY_PORT_CONFIG, &phy_data);
    			if (ret_val)
    				return ret_val;
    			phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
    			ret_val = e1000_write_phy_reg(hw,
    					IGP01E1000_PHY_PORT_CONFIG, phy_data);
    			if (ret_val)
    				return ret_val;
    			/* Set auto Master/Slave resolution process */
    			ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
    					&phy_data);
    			if (ret_val)
    				return ret_val;
    			phy_data &= ~CR_1000T_MS_ENABLE;
    			ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
    					phy_data);
    			if (ret_val)
    				return ret_val;
    		}
    
    		ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
    		if (ret_val)
    			return ret_val;
    
    		/* load defaults for future use */
    		hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
    				((phy_data & CR_1000T_MS_VALUE) ?
    				e1000_ms_force_master :
    				e1000_ms_force_slave) :
    				e1000_ms_auto;
    
    		switch (phy_ms_setting) {
    		case e1000_ms_force_master:
    			phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
    			break;
    		case e1000_ms_force_slave:
    			phy_data |= CR_1000T_MS_ENABLE;
    			phy_data &= ~(CR_1000T_MS_VALUE);
    			break;
    		case e1000_ms_auto:
    			phy_data &= ~CR_1000T_MS_ENABLE;
    		default:
    			break;
    		}
    		ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
    		if (ret_val)
    			return ret_val;
    	}
    
    	return E1000_SUCCESS;
    }
    
    /*****************************************************************************
     * This function checks the mode of the firmware.
     *
     * returns  - TRUE when the mode is IAMT or FALSE.
     ****************************************************************************/
    boolean_t
    e1000_check_mng_mode(struct e1000_hw *hw)
    {
    	uint32_t fwsm;
    	DEBUGFUNC();
    
    	fwsm = E1000_READ_REG(hw, FWSM);
    
    	if (hw->mac_type == e1000_ich8lan) {
    		if ((fwsm & E1000_FWSM_MODE_MASK) ==
    		    (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
    			return TRUE;
    	} else if ((fwsm & E1000_FWSM_MODE_MASK) ==
    		       (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
    			return TRUE;
    
    	return FALSE;
    }
    
    static int32_t
    e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
    {
    
    	uint16_t swfw = E1000_SWFW_PHY0_SM;
    
    	uint32_t reg_val;
    	DEBUGFUNC();
    
    
    	if (e1000_is_second_port(hw))
    
    		swfw = E1000_SWFW_PHY1_SM;
    
    	if (e1000_swfw_sync_acquire(hw, swfw))
    		return -E1000_ERR_SWFW_SYNC;
    
    	reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
    			& E1000_KUMCTRLSTA_OFFSET) | data;
    	E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
    	udelay(2);
    
    	return E1000_SUCCESS;
    }
    
    static int32_t
    e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
    {
    
    	uint16_t swfw = E1000_SWFW_PHY0_SM;
    
    	uint32_t reg_val;
    	DEBUGFUNC();
    
    
    	if (e1000_is_second_port(hw))
    
    		swfw = E1000_SWFW_PHY1_SM;
    
    	if (e1000_swfw_sync_acquire(hw, swfw))
    		return -E1000_ERR_SWFW_SYNC;
    
    	/* Write register address */
    	reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
    			E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
    	E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
    	udelay(2);
    
    	/* Read the data returned */
    	reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
    	*data = (uint16_t)reg_val;
    
    	return E1000_SUCCESS;
    }
    
    /********************************************************************
    * Copper link setup for e1000_phy_gg82563 series.
    *
    * hw - Struct containing variables accessed by shared code
    *********************************************************************/
    static int32_t
    e1000_copper_link_ggp_setup(struct e1000_hw *hw)
    {
    	int32_t ret_val;
    	uint16_t phy_data;
    	uint32_t reg_data;
    
    	DEBUGFUNC();
    
    	if (!hw->phy_reset_disable) {
    		/* Enable CRS on TX for half-duplex operation. */
    		ret_val = e1000_read_phy_reg(hw,
    				GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
    		if (ret_val)
    			return ret_val;
    
    		phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
    		/* Use 25MHz for both link down and 1000BASE-T for Tx clock */
    		phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
    
    		ret_val = e1000_write_phy_reg(hw,
    				GG82563_PHY_MAC_SPEC_CTRL, phy_data);
    		if (ret_val)
    			return ret_val;
    
    		/* Options:
    		 *   MDI/MDI-X = 0 (default)
    		 *   0 - Auto for all speeds
    		 *   1 - MDI mode
    		 *   2 - MDI-X mode
    		 *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
    		 */
    		ret_val = e1000_read_phy_reg(hw,
    				GG82563_PHY_SPEC_CTRL, &phy_data);
    		if (ret_val)
    			return ret_val;
    
    		phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
    
    		switch (hw->mdix) {
    		case 1:
    			phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
    			break;
    		case 2:
    			phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
    			break;
    		case 0:
    		default:
    			phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
    			break;
    		}
    
    		/* Options:
    		 *   disable_polarity_correction = 0 (default)
    		 *       Automatic Correction for Reversed Cable Polarity
    		 *   0 - Disabled
    		 *   1 - Enabled
    		 */
    		phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
    		ret_val = e1000_write_phy_reg(hw,
    				GG82563_PHY_SPEC_CTRL, phy_data);
    
    		if (ret_val)
    			return ret_val;
    
    		/* SW Reset the PHY so all changes take effect */
    		ret_val = e1000_phy_reset(hw);
    		if (ret_val) {
    			DEBUGOUT("Error Resetting the PHY\n");
    			return ret_val;
    		}
    	} /* phy_reset_disable */
    
    	if (hw->mac_type == e1000_80003es2lan) {
    		/* Bypass RX and TX FIFO's */
    		ret_val = e1000_write_kmrn_reg(hw,
    				E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
    				E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
    				| E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
    		if (ret_val)
    			return ret_val;
    
    		ret_val = e1000_read_phy_reg(hw,
    				GG82563_PHY_SPEC_CTRL_2, &phy_data);
    		if (ret_val)
    			return ret_val;
    
    		phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
    		ret_val = e1000_write_phy_reg(hw,
    				GG82563_PHY_SPEC_CTRL_2, phy_data);
    
    		if (ret_val)
    			return ret_val;
    
    		reg_data = E1000_READ_REG(hw, CTRL_EXT);
    		reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
    		E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
    
    		ret_val = e1000_read_phy_reg(hw,
    				GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
    		if (ret_val)
    			return ret_val;
    
    	/* Do not init these registers when the HW is in IAMT mode, since the
    	 * firmware will have already initialized them.  We only initialize
    	 * them if the HW is not in IAMT mode.
    	 */
    		if (e1000_check_mng_mode(hw) == FALSE) {
    			/* Enable Electrical Idle on the PHY */
    			phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
    			ret_val = e1000_write_phy_reg(hw,
    					GG82563_PHY_PWR_MGMT_CTRL, phy_data);
    			if (ret_val)
    				return ret_val;
    
    			ret_val = e1000_read_phy_reg(hw,
    					GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
    			if (ret_val)
    				return ret_val;
    
    			phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
    			ret_val = e1000_write_phy_reg(hw,
    					GG82563_PHY_KMRN_MODE_CTRL, phy_data);
    
    			if (ret_val)
    				return ret_val;
    		}
    
    		/* Workaround: Disable padding in Kumeran interface in the MAC
    		 * and in the PHY to avoid CRC errors.
    		 */
    		ret_val = e1000_read_phy_reg(hw,
    				GG82563_PHY_INBAND_CTRL, &phy_data);
    		if (ret_val)
    			return ret_val;
    		phy_data |= GG82563_ICR_DIS_PADDING;
    		ret_val = e1000_write_phy_reg(hw,
    				GG82563_PHY_INBAND_CTRL, phy_data);
    		if (ret_val)
    			return ret_val;
    
    	return E1000_SUCCESS;
    
    /********************************************************************
    * Copper link setup for e1000_phy_m88 series.
    
    *
    * hw - Struct containing variables accessed by shared code
    
    *********************************************************************/
    static int32_t
    e1000_copper_link_mgp_setup(struct e1000_hw *hw)
    
    {
    	int32_t ret_val;
    	uint16_t phy_data;
    
    	DEBUGFUNC();
    
    
    	if (hw->phy_reset_disable)
    		return E1000_SUCCESS;
    
    	/* Enable CRS on TX. This must be set for half-duplex operation. */
    	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
    	if (ret_val)
    
    		return ret_val;
    
    	phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
    
    	/* Options:
    	 *   MDI/MDI-X = 0 (default)
    	 *   0 - Auto for all speeds
    	 *   1 - MDI mode
    	 *   2 - MDI-X mode
    	 *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
    	 */
    	phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
    
    	switch (hw->mdix) {
    	case 1:
    		phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
    		break;
    	case 2:
    		phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
    		break;
    	case 3:
    		phy_data |= M88E1000_PSCR_AUTO_X_1000T;
    		break;
    	case 0:
    	default:
    		phy_data |= M88E1000_PSCR_AUTO_X_MODE;
    		break;
    	}
    
    	/* Options:
    	 *   disable_polarity_correction = 0 (default)
    
    	 *       Automatic Correction for Reversed Cable Polarity
    
    	 *   0 - Disabled
    	 *   1 - Enabled
    	 */
    	phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
    
    	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
    	if (ret_val)
    		return ret_val;
    
    	if (hw->phy_revision < M88E1011_I_REV_4) {
    		/* Force TX_CLK in the Extended PHY Specific Control Register
    		 * to 25MHz clock.
    		 */
    		ret_val = e1000_read_phy_reg(hw,
    				M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
    		if (ret_val)
    			return ret_val;
    
    		phy_data |= M88E1000_EPSCR_TX_CLK_25;
    
    		if ((hw->phy_revision == E1000_REVISION_2) &&
    			(hw->phy_id == M88E1111_I_PHY_ID)) {
    			/* Vidalia Phy, set the downshift counter to 5x */
    			phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
    			phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
    			ret_val = e1000_write_phy_reg(hw,
    					M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
    			if (ret_val)
    				return ret_val;
    		} else {
    			/* Configure Master and Slave downshift values */
    			phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
    					| M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
    			phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
    					| M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
    			ret_val = e1000_write_phy_reg(hw,
    					M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
    			if (ret_val)
    				return ret_val;
    		}
    
    	}
    
    	/* SW Reset the PHY so all changes take effect */
    	ret_val = e1000_phy_reset(hw);
    
    	if (ret_val) {
    
    		DEBUGOUT("Error Resetting the PHY\n");
    		return ret_val;
    	}
    
    
    	return E1000_SUCCESS;
    }
    
    /********************************************************************
    * Setup auto-negotiation and flow control advertisements,
    * and then perform auto-negotiation.
    *
    * hw - Struct containing variables accessed by shared code
    *********************************************************************/
    static int32_t
    e1000_copper_link_autoneg(struct e1000_hw *hw)
    {
    	int32_t ret_val;
    	uint16_t phy_data;
    
    	DEBUGFUNC();
    
    
    	/* Perform some bounds checking on the hw->autoneg_advertised
    	 * parameter.  If this variable is zero, then set it to the default.
    	 */
    	hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
    
    	/* If autoneg_advertised is zero, we assume it was not defaulted
    	 * by the calling code so we set to advertise full capability.
    	 */
    	if (hw->autoneg_advertised == 0)
    		hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
    
    
    	/* IFE phy only supports 10/100 */
    	if (hw->phy_type == e1000_phy_ife)
    		hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
    
    
    	DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
    	ret_val = e1000_phy_setup_autoneg(hw);
    
    	if (ret_val) {
    
    		DEBUGOUT("Error Setting up Auto-Negotiation\n");
    		return ret_val;
    	}
    	DEBUGOUT("Restarting Auto-Neg\n");
    
    	/* Restart auto-negotiation by setting the Auto Neg Enable bit and
    	 * the Auto Neg Restart bit in the PHY control register.
    	 */
    
    	ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
    	if (ret_val)
    		return ret_val;
    
    
    	phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
    
    	ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
    	if (ret_val)
    		return ret_val;
    
    
    	/* Does the user want to wait for Auto-Neg to complete here, or
    	 * check at a later time (for example, callback routine).
    	 */
    
    	/* If we do not wait for autonegtation to complete I
    	 * do not see a valid link status.
    	 * wait_autoneg_complete = 1 .
    	 */
    
    	if (hw->wait_autoneg_complete) {
    		ret_val = e1000_wait_autoneg(hw);
    
    		if (ret_val) {
    			DEBUGOUT("Error while waiting for autoneg"
    					"to complete\n");
    
    
    	hw->get_link_status = TRUE;
    
    	return E1000_SUCCESS;
    }
    
    /******************************************************************************
    * Config the MAC and the PHY after link is up.
    *   1) Set up the MAC to the current PHY speed/duplex
    *      if we are on 82543.  If we
    *      are on newer silicon, we only need to configure
    *      collision distance in the Transmit Control Register.
    *   2) Set up flow control on the MAC to that established with
    *      the link partner.
    *   3) Config DSP to improve Gigabit link quality for some PHY revisions.
    *
    * hw - Struct containing variables accessed by shared code
    ******************************************************************************/
    static int32_t
    e1000_copper_link_postconfig(struct e1000_hw *hw)
    {
    	int32_t ret_val;
    	DEBUGFUNC();
    
    	if (hw->mac_type >= e1000_82544) {
    		e1000_config_collision_dist(hw);
    	} else {
    		ret_val = e1000_config_mac_to_phy(hw);
    		if (ret_val) {
    			DEBUGOUT("Error configuring MAC to PHY settings\n");
    			return ret_val;
    		}
    	}
    	ret_val = e1000_config_fc_after_link_up(hw);
    	if (ret_val) {
    		DEBUGOUT("Error Configuring Flow Control\n");
    
    	return E1000_SUCCESS;
    }
    
    /******************************************************************************
    * Detects which PHY is present and setup the speed and duplex
    *
    * hw - Struct containing variables accessed by shared code
    ******************************************************************************/
    static int
    e1000_setup_copper_link(struct eth_device *nic)
    {
    	struct e1000_hw *hw = nic->priv;
    	int32_t ret_val;
    	uint16_t i;
    	uint16_t phy_data;
    	uint16_t reg_data;
    
    	DEBUGFUNC();
    
    	switch (hw->mac_type) {
    	case e1000_80003es2lan:
    	case e1000_ich8lan:
    		/* Set the mac to wait the maximum time between each
    		 * iteration and increase the max iterations when
    		 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
    		ret_val = e1000_write_kmrn_reg(hw,
    				GG82563_REG(0x34, 4), 0xFFFF);
    		if (ret_val)
    			return ret_val;
    		ret_val = e1000_read_kmrn_reg(hw,
    				GG82563_REG(0x34, 9), &reg_data);
    		if (ret_val)
    			return ret_val;
    		reg_data |= 0x3F;
    		ret_val = e1000_write_kmrn_reg(hw,
    				GG82563_REG(0x34, 9), reg_data);
    		if (ret_val)
    			return ret_val;
    	default:
    		break;
    	}
    
    	/* Check if it is a valid PHY and set PHY mode if necessary. */
    	ret_val = e1000_copper_link_preconfig(hw);
    	if (ret_val)
    		return ret_val;
    	switch (hw->mac_type) {
    	case e1000_80003es2lan:
    		/* Kumeran registers are written-only */
    		reg_data =
    		E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
    		reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
    		ret_val = e1000_write_kmrn_reg(hw,
    				E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
    		if (ret_val)
    			return ret_val;
    		break;
    	default:
    		break;
    	}
    
    	if (hw->phy_type == e1000_phy_igp ||
    		hw->phy_type == e1000_phy_igp_3 ||
    		hw->phy_type == e1000_phy_igp_2) {
    		ret_val = e1000_copper_link_igp_setup(hw);
    		if (ret_val)
    			return ret_val;
    	} else if (hw->phy_type == e1000_phy_m88) {
    		ret_val = e1000_copper_link_mgp_setup(hw);
    		if (ret_val)
    			return ret_val;
    	} else if (hw->phy_type == e1000_phy_gg82563) {
    		ret_val = e1000_copper_link_ggp_setup(hw);
    		if (ret_val)
    			return ret_val;
    	}
    
    	/* always auto */
    	/* Setup autoneg and flow control advertisement
    	  * and perform autonegotiation */
    	ret_val = e1000_copper_link_autoneg(hw);
    	if (ret_val)
    		return ret_val;
    
    
    	/* Check link status. Wait up to 100 microseconds for link to become
    	 * valid.
    	 */
    	for (i = 0; i < 10; i++) {
    
    		ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
    		if (ret_val)
    			return ret_val;
    		ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);