cmd_i2c.c

		case 0:  puts ("TTL 5.0 V\n");	break;
		case 1:  puts ("LVTTL\n");	break;
		case 2:  puts ("HSTL 1.5 V\n");	break;
		case 3:  puts ("SSTL 3.3 V\n");	break;
		case 4:  puts ("SSTL 2.5 V\n");	break;
		case 5:  puts ("SSTL 1.8 V\n");	break;
		default: puts ("unknown\n");	break;
	}

	switch (type) {
	case DDR2:
		printf ("SDRAM cycle time             ");
		print_ddr2_tcyc (data[9]);
		break;
	default:
		printf ("SDRAM cycle time             %d.%d ns\n",
			(data[9] >> 4) & 0x0F, data[9] & 0x0F);
		break;
	}

	switch (type) {
	case DDR2:
		printf ("SDRAM access time            0.%d%d ns\n",
			(data[10] >> 4) & 0x0F, data[10] & 0x0F);
		break;
	default:
		printf ("SDRAM access time            %d.%d ns\n",
			(data[10] >> 4) & 0x0F, data[10] & 0x0F);
		break;
	}

	puts ("EDC configuration            ");
	switch (data[11]) {
		case 0:  puts ("None\n");	break;
		case 1:  puts ("Parity\n");	break;
		case 2:  puts ("ECC\n");	break;
		default: puts ("unknown\n");	break;
	}

	if ((data[12] & 0x80) == 0)
		puts ("No self refresh, rate        ");
	else
		puts ("Self refresh, rate           ");

	switch(data[12] & 0x7F) {
		case 0:  puts ("15.625 us\n");	break;
		case 1:  puts ("3.9 us\n");	break;
		case 2:  puts ("7.8 us\n");	break;
		case 3:  puts ("31.3 us\n");	break;
		case 4:  puts ("62.5 us\n");	break;
		case 5:  puts ("125 us\n");	break;
		default: puts ("unknown\n");	break;
	}

	switch (type) {
	case DDR2:
		printf ("SDRAM width (primary)        %d\n", data[13]);
		break;
	default:
		printf ("SDRAM width (primary)        %d\n", data[13] & 0x7F);
		if ((data[13] & 0x80) != 0) {
			printf ("  (second bank)              %d\n",
				2 * (data[13] & 0x7F));
		}
		break;
	}

	switch (type) {
	case DDR2:
		if (data[14] != 0)
			printf ("EDC width                    %d\n", data[14]);
		break;
	default:
		if (data[14] != 0) {
			printf ("EDC width                    %d\n",
				data[14] & 0x7F);

			if ((data[14] & 0x80) != 0) {
				printf ("  (second bank)              %d\n",
					2 * (data[14] & 0x7F));
			}
		}
		break;
	}

	if (DDR2 != type) {
		printf ("Min clock delay, back-to-back random column addresses "
			"%d\n", data[15]);
	}

	puts ("Burst length(s)             ");
	if (data[16] & 0x80) puts (" Page");
	if (data[16] & 0x08) puts (" 8");
	if (data[16] & 0x04) puts (" 4");
	if (data[16] & 0x02) puts (" 2");
	if (data[16] & 0x01) puts (" 1");
	putc ('\n');
	printf ("Number of banks              %d\n", data[17]);

	switch (type) {
	case DDR2:
		puts ("CAS latency(s)              ");
		decode_bits (data[18], decode_CAS_DDR2, 0);
		putc ('\n');
		break;
	default:
		puts ("CAS latency(s)              ");
		decode_bits (data[18], decode_CAS_default, 0);
		putc ('\n');
		break;
	}

	if (DDR2 != type) {
		puts ("CS latency(s)               ");
		decode_bits (data[19], decode_CS_WE_default, 0);
		putc ('\n');
	}

	if (DDR2 != type) {
		puts ("WE latency(s)               ");
		decode_bits (data[20], decode_CS_WE_default, 0);
		putc ('\n');
	}

	switch (type) {
	case DDR2:
		puts ("Module attributes:\n");
		if (data[21] & 0x80)
			puts ("  TBD (bit 7)\n");
		if (data[21] & 0x40)
			puts ("  Analysis probe installed\n");
		if (data[21] & 0x20)
			puts ("  TBD (bit 5)\n");
		if (data[21] & 0x10)
			puts ("  FET switch external enable\n");
		printf ("  %d PLLs on DIMM\n", (data[21] >> 2) & 0x03);
		if (data[20] & 0x11) {
			printf ("  %d active registers on DIMM\n",
				(data[21] & 0x03) + 1);
		}
		break;
	default:
		puts ("Module attributes:\n");
		if (!data[21])
			puts ("  (none)\n");
		else
			decode_bits (data[21], decode_byte21_default, 0);
		break;
	}

	switch (type) {
	case DDR2:
		decode_bits (data[22], decode_byte22_DDR2, 0);
		break;
	default:
		puts ("Device attributes:\n");
		if (data[22] & 0x80) puts ("  TBD (bit 7)\n");
		if (data[22] & 0x40) puts ("  TBD (bit 6)\n");
		if (data[22] & 0x20) puts ("  Upper Vcc tolerance 5%\n");
		else                 puts ("  Upper Vcc tolerance 10%\n");
		if (data[22] & 0x10) puts ("  Lower Vcc tolerance 5%\n");
		else                 puts ("  Lower Vcc tolerance 10%\n");
		if (data[22] & 0x08) puts ("  Supports write1/read burst\n");
		if (data[22] & 0x04) puts ("  Supports precharge all\n");
		if (data[22] & 0x02) puts ("  Supports auto precharge\n");
		if (data[22] & 0x01) puts ("  Supports early RAS# precharge\n");
		break;
	}

	switch (type) {
	case DDR2:
		printf ("SDRAM cycle time (2nd highest CAS latency)        ");
		print_ddr2_tcyc (data[23]);
		break;
	default:
		printf ("SDRAM cycle time (2nd highest CAS latency)        %d."
			"%d ns\n", (data[23] >> 4) & 0x0F, data[23] & 0x0F);
		break;
	}

	switch (type) {
	case DDR2:
		printf ("SDRAM access from clock (2nd highest CAS latency) 0."
			"%d%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
		break;
	default:
		printf ("SDRAM access from clock (2nd highest CAS latency) %d."
			"%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
		break;
	}

	switch (type) {
	case DDR2:
		printf ("SDRAM cycle time (3rd highest CAS latency)        ");
		print_ddr2_tcyc (data[25]);
		break;
	default:
		printf ("SDRAM cycle time (3rd highest CAS latency)        %d."
			"%d ns\n", (data[25] >> 4) & 0x0F, data[25] & 0x0F);
		break;
	}

	switch (type) {
	case DDR2:
		printf ("SDRAM access from clock (3rd highest CAS latency) 0."
			"%d%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
		break;
	default:
		printf ("SDRAM access from clock (3rd highest CAS latency) %d."
			"%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
		break;
	}

	switch (type) {
	case DDR2:
		printf ("Minimum row precharge        %d.%02d ns\n",
			(data[27] >> 2) & 0x3F, 25 * (data[27] & 0x03));
		break;
	default:
		printf ("Minimum row precharge        %d ns\n", data[27]);
		break;
	}

	switch (type) {
	case DDR2:
		printf ("Row active to row active min %d.%02d ns\n",
			(data[28] >> 2) & 0x3F, 25 * (data[28] & 0x03));
		break;
	default:
		printf ("Row active to row active min %d ns\n", data[28]);
		break;
	}

	switch (type) {
	case DDR2:
		printf ("RAS to CAS delay min         %d.%02d ns\n",
			(data[29] >> 2) & 0x3F, 25 * (data[29] & 0x03));
		break;
	default:
		printf ("RAS to CAS delay min         %d ns\n", data[29]);
		break;
	}

	printf ("Minimum RAS pulse width      %d ns\n", data[30]);

	switch (type) {
	case DDR2:
		puts ("Density of each row          ");
		decode_bits (data[31], decode_row_density_DDR2, 1);
		putc ('\n');
		break;
	default:
		puts ("Density of each row          ");
		decode_bits (data[31], decode_row_density_default, 1);
		putc ('\n');
		break;
	}

	switch (type) {
	case DDR2:
		puts ("Command and Address setup    ");
		if (data[32] >= 0xA0) {
			printf ("1.%d%d ns\n",
				((data[32] >> 4) & 0x0F) - 10, data[32] & 0x0F);
		} else {
			printf ("0.%d%d ns\n",
				((data[32] >> 4) & 0x0F), data[32] & 0x0F);
		}
		break;
	default:
		printf ("Command and Address setup    %c%d.%d ns\n",
			(data[32] & 0x80) ? '-' : '+',
			(data[32] >> 4) & 0x07, data[32] & 0x0F);
		break;
	}

	switch (type) {
	case DDR2:
		puts ("Command and Address hold     ");
		if (data[33] >= 0xA0) {
			printf ("1.%d%d ns\n",
				((data[33] >> 4) & 0x0F) - 10, data[33] & 0x0F);
		} else {
			printf ("0.%d%d ns\n",
				((data[33] >> 4) & 0x0F), data[33] & 0x0F);
		}
		break;
	default:
		printf ("Command and Address hold     %c%d.%d ns\n",
			(data[33] & 0x80) ? '-' : '+',
			(data[33] >> 4) & 0x07, data[33] & 0x0F);
		break;
	}

	switch (type) {
	case DDR2:
		printf ("Data signal input setup      0.%d%d ns\n",
			(data[34] >> 4) & 0x0F, data[34] & 0x0F);
		break;
	default:
		printf ("Data signal input setup      %c%d.%d ns\n",
			(data[34] & 0x80) ? '-' : '+',
			(data[34] >> 4) & 0x07, data[34] & 0x0F);
		break;
	}

	switch (type) {
	case DDR2:
		printf ("Data signal input hold       0.%d%d ns\n",
			(data[35] >> 4) & 0x0F, data[35] & 0x0F);
		break;
	default:
		printf ("Data signal input hold       %c%d.%d ns\n",
			(data[35] & 0x80) ? '-' : '+',
			(data[35] >> 4) & 0x07, data[35] & 0x0F);
		break;
	}

	puts ("Manufacturer's JEDEC ID      ");
	for (j = 64; j <= 71; j++)
		printf ("%02X ", data[j]);
	putc ('\n');
	printf ("Manufacturing Location       %02X\n", data[72]);
	puts ("Manufacturer's Part Number   ");
	for (j = 73; j <= 90; j++)
		printf ("%02X ", data[j]);
	putc ('\n');
	printf ("Revision Code                %02X %02X\n", data[91], data[92]);
	printf ("Manufacturing Date           %02X %02X\n", data[93], data[94]);
	puts ("Assembly Serial Number       ");
	for (j = 95; j <= 98; j++)
		printf ("%02X ", data[j]);
	putc ('\n');

	if (DDR2 != type) {
		printf ("Speed rating                 PC%d\n",
			data[126] == 0x66 ? 66 : data[126]);
	}
	return 0;
}
#endif

#if defined(CONFIG_I2C_MUX)
/**
 * do_i2c_add_bus() - Handle the "i2c bus" command-line command
 * @cmdtp:	Command data struct pointer
 * @flag:	Command flag
 * @argc:	Command-line argument count
 * @argv:	Array of command-line arguments
 *
 * Returns zero always.
 */
static int do_i2c_add_bus(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
	int ret=0;

	if (argc == 1) {
		/* show all busses */
		I2C_MUX		*mux;
		I2C_MUX_DEVICE	*device = i2c_mux_devices;

		printf ("Busses reached over muxes:\n");
		while (device != NULL) {
			printf ("Bus ID: %x\n", device->busid);
			printf ("  reached over Mux(es):\n");
			mux = device->mux;
			while (mux != NULL) {
				printf ("    %s@%x ch: %x\n", mux->name, mux->chip, mux->channel);
				mux = mux->next;
			}
			device = device->next;
		}
	} else {
		(void)i2c_mux_ident_muxstring ((uchar *)argv[1]);
		ret = 0;
	}
	return ret;
}
#endif  /* CONFIG_I2C_MUX */

#if defined(CONFIG_I2C_MULTI_BUS)
/**
 * do_i2c_bus_num() - Handle the "i2c dev" command-line command
 * @cmdtp:	Command data struct pointer
 * @flag:	Command flag
 * @argc:	Command-line argument count
 * @argv:	Array of command-line arguments
 *
 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
 * on error.
 */
static int do_i2c_bus_num(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
	int bus_idx, ret=0;

	if (argc == 1)
		/* querying current setting */
		printf("Current bus is %d\n", i2c_get_bus_num());
	else {
		bus_idx = simple_strtoul(argv[1], NULL, 10);
		printf("Setting bus to %d\n", bus_idx);
		ret = i2c_set_bus_num(bus_idx);
		if (ret)
			printf("Failure changing bus number (%d)\n", ret);
	}
	return ret;
}
#endif  /* CONFIG_I2C_MULTI_BUS */

/**
 * do_i2c_bus_speed() - Handle the "i2c speed" command-line command
 * @cmdtp:	Command data struct pointer
 * @flag:	Command flag
 * @argc:	Command-line argument count
 * @argv:	Array of command-line arguments
 *
 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
 * on error.
 */
static int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
	int speed, ret=0;

	if (argc == 1)
		/* querying current speed */
		printf("Current bus speed=%d\n", i2c_get_bus_speed());
	else {
		speed = simple_strtoul(argv[1], NULL, 10);
		printf("Setting bus speed to %d Hz\n", speed);
		ret = i2c_set_bus_speed(speed);
		if (ret)
			printf("Failure changing bus speed (%d)\n", ret);
	}
	return ret;
}

/**
 * do_i2c_mm() - Handle the "i2c mm" command-line command
 * @cmdtp:	Command data struct pointer
 * @flag:	Command flag
 * @argc:	Command-line argument count
 * @argv:	Array of command-line arguments
 *
 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
 * on error.
 */
static int do_i2c_mm(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
	return mod_i2c_mem (cmdtp, 1, flag, argc, argv);
}

/**
 * do_i2c_nm() - Handle the "i2c nm" command-line command
 * @cmdtp:	Command data struct pointer
 * @flag:	Command flag
 * @argc:	Command-line argument count
 * @argv:	Array of command-line arguments
 *
 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
 * on error.
 */
static int do_i2c_nm(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
	return mod_i2c_mem (cmdtp, 0, flag, argc, argv);
}

/**
 * do_i2c_reset() - Handle the "i2c reset" command-line command
 * @cmdtp:	Command data struct pointer
 * @flag:	Command flag
 * @argc:	Command-line argument count
 * @argv:	Array of command-line arguments
 *
 * Returns zero always.
 */
static int do_i2c_reset(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
	return 0;
}

static cmd_tbl_t cmd_i2c_sub[] = {
#if defined(CONFIG_I2C_MUX)
	U_BOOT_CMD_MKENT(bus, 1, 1, do_i2c_add_bus, "", ""),
#endif  /* CONFIG_I2C_MUX */
	U_BOOT_CMD_MKENT(crc32, 3, 1, do_i2c_crc, "", ""),
#if defined(CONFIG_I2C_MULTI_BUS)
	U_BOOT_CMD_MKENT(dev, 1, 1, do_i2c_bus_num, "", ""),
#endif  /* CONFIG_I2C_MULTI_BUS */
	U_BOOT_CMD_MKENT(loop, 3, 1, do_i2c_loop, "", ""),
	U_BOOT_CMD_MKENT(md, 3, 1, do_i2c_md, "", ""),
	U_BOOT_CMD_MKENT(mm, 2, 1, do_i2c_mm, "", ""),
	U_BOOT_CMD_MKENT(mw, 3, 1, do_i2c_mw, "", ""),
	U_BOOT_CMD_MKENT(nm, 2, 1, do_i2c_nm, "", ""),
	U_BOOT_CMD_MKENT(probe, 0, 1, do_i2c_probe, "", ""),
	U_BOOT_CMD_MKENT(read, 5, 1, do_i2c_read, "", ""),
	U_BOOT_CMD_MKENT(write, 5, 0, do_i2c_write, "", ""),
	U_BOOT_CMD_MKENT(reset, 0, 1, do_i2c_reset, "", ""),
#if defined(CONFIG_CMD_SDRAM)
	U_BOOT_CMD_MKENT(sdram, 1, 1, do_sdram, "", ""),
#endif
	U_BOOT_CMD_MKENT(speed, 1, 1, do_i2c_bus_speed, "", ""),
};

#ifdef CONFIG_NEEDS_MANUAL_RELOC
void i2c_reloc(void) {
	fixup_cmdtable(cmd_i2c_sub, ARRAY_SIZE(cmd_i2c_sub));
}
#endif

/**
 * do_i2c() - Handle the "i2c" command-line command
 * @cmdtp:	Command data struct pointer
 * @flag:	Command flag
 * @argc:	Command-line argument count
 * @argv:	Array of command-line arguments
 *
 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
 * on error.
 */
static int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
	cmd_tbl_t *c;

	if (argc < 2)
		return CMD_RET_USAGE;

	/* Strip off leading 'i2c' command argument */
	argc--;
	argv++;

	c = find_cmd_tbl(argv[0], &cmd_i2c_sub[0], ARRAY_SIZE(cmd_i2c_sub));

	if (c)
		return c->cmd(cmdtp, flag, argc, argv);
	else
		return CMD_RET_USAGE;
}

/***************************************************/
#ifdef CONFIG_SYS_LONGHELP
static char i2c_help_text[] =
#if defined(CONFIG_I2C_MUX)
	"bus [muxtype:muxaddr:muxchannel] - add a new bus reached over muxes\ni2c "
#endif  /* CONFIG_I2C_MUX */
	"crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
#if defined(CONFIG_I2C_MULTI_BUS)
	"i2c dev [dev] - show or set current I2C bus\n"
#endif  /* CONFIG_I2C_MULTI_BUS */
	"i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device\n"
	"i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n"
	"i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n"
	"i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n"
	"i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n"
	"i2c probe [address] - test for and show device(s) on the I2C bus\n"
	"i2c read chip address[.0, .1, .2] length memaddress - read to memory \n"
	"i2c write memaddress chip address[.0, .1, .2] length - write memory to i2c\n"
	"i2c reset - re-init the I2C Controller\n"
#if defined(CONFIG_CMD_SDRAM)
	"i2c sdram chip - print SDRAM configuration information\n"
#endif
	"i2c speed [speed] - show or set I2C bus speed";
#endif

U_BOOT_CMD(
	i2c, 6, 1, do_i2c,
	"I2C sub-system",
	i2c_help_text
);

#if defined(CONFIG_I2C_MUX)
static int i2c_mux_add_device(I2C_MUX_DEVICE *dev)
{
	I2C_MUX_DEVICE	*devtmp = i2c_mux_devices;

	if (i2c_mux_devices == NULL) {
		i2c_mux_devices = dev;
		return 0;
	}
	while (devtmp->next != NULL)
		devtmp = devtmp->next;

	devtmp->next = dev;
	return 0;
}

I2C_MUX_DEVICE	*i2c_mux_search_device(int id)
{
	I2C_MUX_DEVICE	*device = i2c_mux_devices;

	while (device != NULL) {
		if (device->busid == id)
			return device;
		device = device->next;
	}
	return NULL;
}

/* searches in the buf from *pos the next ':'.
 * returns:
 *     0 if found (with *pos = where)
 *   < 0 if an error occured
 *   > 0 if the end of buf is reached
 */
static int i2c_mux_search_next (int *pos, uchar	*buf, int len)
{
	while ((buf[*pos] != ':') && (*pos < len)) {
		*pos += 1;
	}
	if (*pos >= len)
		return 1;
	if (buf[*pos] != ':')
		return -1;
	return 0;
}

static int i2c_mux_get_busid (void)
{
	int	tmp = i2c_mux_busid;

	i2c_mux_busid ++;
	return tmp;
}

/* Analyses a Muxstring and immediately sends the
   commands to the muxes. Runs from flash.
 */
int i2c_mux_ident_muxstring_f (uchar *buf)
{
	int	pos = 0;
	int	oldpos;
	int	ret = 0;
	int	len = strlen((char *)buf);
	int	chip;
	uchar	channel;
	int	was = 0;

	while (ret == 0) {
		oldpos = pos;
		/* search name */
		ret = i2c_mux_search_next(&pos, buf, len);
		if (ret != 0)
			printf ("ERROR\n");
		/* search address */
		pos ++;
		oldpos = pos;
		ret = i2c_mux_search_next(&pos, buf, len);
		if (ret != 0)
			printf ("ERROR\n");
		buf[pos] = 0;
		chip = simple_strtoul((char *)&buf[oldpos], NULL, 16);
		buf[pos] = ':';
		/* search channel */
		pos ++;
		oldpos = pos;
		ret = i2c_mux_search_next(&pos, buf, len);
		if (ret < 0)
			printf ("ERROR\n");
		was = 0;
		if (buf[pos] != 0) {
			buf[pos] = 0;
			was = 1;
		}
		channel = simple_strtoul((char *)&buf[oldpos], NULL, 16);
		if (was)
			buf[pos] = ':';
		if (i2c_write(chip, 0, 0, &channel, 1) != 0) {
			printf ("Error setting Mux: chip:%x channel: \
				%x\n", chip, channel);
			return -1;
		}
		pos ++;
		oldpos = pos;

	}
	i2c_init_board();

	return 0;
}

/* Analyses a Muxstring and if this String is correct
 * adds a new I2C Bus.
 */
I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf)
{
	I2C_MUX_DEVICE	*device;
	I2C_MUX		*mux;
	int	pos = 0;
	int	oldpos;
	int	ret = 0;
	int	len = strlen((char *)buf);
	int	was = 0;

	device = (I2C_MUX_DEVICE *)malloc (sizeof(I2C_MUX_DEVICE));
	device->mux = NULL;
	device->busid = i2c_mux_get_busid ();
	device->next = NULL;
	while (ret == 0) {
		mux = (I2C_MUX *)malloc (sizeof(I2C_MUX));
		mux->next = NULL;
		/* search name of mux */
		oldpos = pos;
		ret = i2c_mux_search_next(&pos, buf, len);
		if (ret != 0)
			printf ("%s no name.\n", __FUNCTION__);
		mux->name = (char *)malloc (pos - oldpos + 1);
		memcpy (mux->name, &buf[oldpos], pos - oldpos);
		mux->name[pos - oldpos] = 0;
		/* search address */
		pos ++;
		oldpos = pos;
		ret = i2c_mux_search_next(&pos, buf, len);
		if (ret != 0)
			printf ("%s no mux address.\n", __FUNCTION__);
		buf[pos] = 0;
		mux->chip = simple_strtoul((char *)&buf[oldpos], NULL, 16);
		buf[pos] = ':';
		/* search channel */
		pos ++;
		oldpos = pos;
		ret = i2c_mux_search_next(&pos, buf, len);
		if (ret < 0)
			printf ("%s no mux channel.\n", __FUNCTION__);
		was = 0;
		if (buf[pos] != 0) {
			buf[pos] = 0;
			was = 1;
		}
		mux->channel = simple_strtoul((char *)&buf[oldpos], NULL, 16);
		if (was)
			buf[pos] = ':';
		if (device->mux == NULL)
			device->mux = mux;
		else {
			I2C_MUX		*muxtmp = device->mux;
			while (muxtmp->next != NULL) {
				muxtmp = muxtmp->next;
			}
			muxtmp->next = mux;
		}
		pos ++;
		oldpos = pos;
	}
	if (ret > 0) {
		/* Add Device */
		i2c_mux_add_device (device);
		return device;
	}

	return NULL;
}

int i2x_mux_select_mux(int bus)
{
	I2C_MUX_DEVICE  *dev;
	I2C_MUX		*mux;

	if ((gd->flags & GD_FLG_RELOC) != GD_FLG_RELOC) {
		/* select Default Mux Bus */
#if defined(CONFIG_SYS_I2C_IVM_BUS)
		i2c_mux_ident_muxstring_f ((uchar *)CONFIG_SYS_I2C_IVM_BUS);
#else
		{
		unsigned char *buf;
		buf = (unsigned char *) getenv("EEprom_ivm");
		if (buf != NULL)
			i2c_mux_ident_muxstring_f (buf);
		}
#endif
		return 0;
	}
	dev = i2c_mux_search_device(bus);
	if (dev == NULL)
		return -1;

	mux = dev->mux;
	while (mux != NULL) {
		/* do deblocking on each level of mux, before mux config */
		i2c_init_board();
		if (i2c_write(mux->chip, 0, 0, &mux->channel, 1) != 0) {
			printf ("Error setting Mux: chip:%x channel: \
				%x\n", mux->chip, mux->channel);
			return -1;
		}
		mux = mux->next;
	}
	/* do deblocking on each level of mux and after mux config */
	i2c_init_board();
	return 0;
}
#endif /* CONFIG_I2C_MUX */