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switch (data[23] & 0x0F) {
case 0x0:
case 0x1:
case 0x2:
case 0x3:
case 0x4:
case 0x5:
case 0x6:
case 0x7:
case 0x8:
case 0x9:
printf("%d ns\n", data[23] & 0x0F);
break;
case 0xA:
puts("25 ns\n");
break;
case 0xB:
puts("33 ns\n");
break;
case 0xC:
puts("66 ns\n");
break;
case 0xD:
puts("75 ns\n");
break;
default:
puts("?? ns\n");
break;
}
break;
default:
printf("SDRAM cycle time (2nd highest CAS latency) %d."
"%d nS\n", (data[23] >> 4) & 0x0F, data[23] & 0x0F);
break;
}
switch (type) {
case DDR2:
printf("SDRAM access from clock (2nd highest CAS latency) 0."
"%d%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
break;
default:
printf("SDRAM access from clock (2nd highest CAS latency) %d."
"%d nS\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
break;
}
switch (type) {
case DDR2:
printf("SDRAM cycle time (3rd highest CAS latency) %d.",
(data[25] >> 4) & 0x0F);
switch (data[25] & 0x0F) {
case 0x0:
case 0x1:
case 0x2:
case 0x3:
case 0x4:
case 0x5:
case 0x6:
case 0x7:
case 0x8:
case 0x9:
printf("%d ns\n", data[25] & 0x0F);
break;
case 0xA:
puts("25 ns\n");
break;
case 0xB:
puts("33 ns\n");
break;
case 0xC:
puts("66 ns\n");
break;
case 0xD:
puts("75 ns\n");
break;
default:
puts("?? ns\n");
break;
}
break;
default:
printf("SDRAM cycle time (3rd highest CAS latency) %d."
"%d nS\n", (data[25] >> 4) & 0x0F, data[25] & 0x0F);
break;
}
switch (type) {
case DDR2:
printf("SDRAM access from clock (3rd highest CAS latency) 0."
"%d%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
break;
default:
printf("SDRAM access from clock (3rd highest CAS latency) %d."
"%d nS\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
break;
}
switch (type) {
case DDR2:
printf("Minimum row precharge %d", data[27] >> 2);
switch (data[27] & 0x03) {
case 0x0: puts(".00 ns\n"); break;
case 0x1: puts(".25 ns\n"); break;
case 0x2: puts(".50 ns\n"); break;
case 0x3: puts(".75 ns\n"); break;
}
break;
default:
printf("Minimum row precharge %d nS\n", data[27]);
break;
}
switch (type) {
case DDR2:
printf("Row active to row active min %d", data[28] >> 2);
switch (data[28] & 0x03) {
case 0x0: puts(".00 ns\n"); break;
case 0x1: puts(".25 ns\n"); break;
case 0x2: puts(".50 ns\n"); break;
case 0x3: puts(".75 ns\n"); break;
}
break;
default:
printf("Row active to row active min %d nS\n", data[28]);
break;
}
switch (type) {
case DDR2:
printf("RAS to CAS delay min %d", data[29] >> 2);
switch (data[29] & 0x03) {
case 0x0: puts(".00 ns\n"); break;
case 0x1: puts(".25 ns\n"); break;
case 0x2: puts(".50 ns\n"); break;
case 0x3: puts(".75 ns\n"); break;
}
break;
default:
printf("RAS to CAS delay min %d nS\n", data[29]);
break;
}
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switch (type) {
case DDR2:
puts ("Density of each row ");
if (data[31] & 0x80) puts (" 512 MiB\n");
if (data[31] & 0x40) puts (" 256 MiB\n");
if (data[31] & 0x20) puts (" 128 MiB\n");
if (data[31] & 0x10) puts (" 16 GiB\n");
if (data[31] & 0x08) puts (" 8 GiB\n");
if (data[31] & 0x04) puts (" 4 GiB\n");
if (data[31] & 0x02) puts (" 2 GiB\n");
if (data[31] & 0x01) puts (" 1 GiB\n");
break;
default:
puts ("Density of each row ");
if (data[31] & 0x80) puts (" 512 MiB\n");
if (data[31] & 0x40) puts (" 256 MiB\n");
if (data[31] & 0x20) puts (" 128 MiB\n");
if (data[31] & 0x10) puts (" 64 MiB\n");
if (data[31] & 0x08) puts (" 32 MiB\n");
if (data[31] & 0x04) puts (" 16 MiB\n");
if (data[31] & 0x02) puts (" 8 MiB\n");
if (data[31] & 0x01) puts (" 4 MiB\n");
break;
}
switch (type) {
case DDR2:
puts("Command and Address setup ");
if (data[32] >= 0xA0) {
printf("1.%d%d ns\n",
((data[32] >> 4) & 0x0F) - 10, data[32] & 0x0F);
} else {
printf("0.%d%d ns\n",
((data[32] >> 4) & 0x0F), data[32] & 0x0F);
}
break;
default:
printf("Command and Address setup %c%d.%d nS\n",
(data[32] & 0x80) ? '-' : '+',
(data[32] >> 4) & 0x07, data[32] & 0x0F);
break;
}
switch (type) {
case DDR2:
puts("Command and Address hold ");
if (data[33] >= 0xA0) {
printf("1.%d%d ns\n",
((data[33] >> 4) & 0x0F) - 10, data[33] & 0x0F);
} else {
printf("0.%d%d ns\n",
((data[33] >> 4) & 0x0F), data[33] & 0x0F);
}
break;
default:
printf("Command and Address hold %c%d.%d nS\n",
(data[33] & 0x80) ? '-' : '+',
(data[33] >> 4) & 0x07, data[33] & 0x0F);
break;
}
switch (type) {
case DDR2:
printf("Data signal input setup 0.%d%d ns\n",
(data[34] >> 4) & 0x0F, data[34] & 0x0F);
break;
default:
printf("Data signal input setup %c%d.%d nS\n",
(data[34] & 0x80) ? '-' : '+',
(data[34] >> 4) & 0x07, data[34] & 0x0F);
break;
}
switch (type) {
case DDR2:
printf("Data signal input hold 0.%d%d ns\n",
(data[35] >> 4) & 0x0F, data[35] & 0x0F);
break;
default:
printf("Data signal input hold %c%d.%d nS\n",
(data[35] & 0x80) ? '-' : '+',
(data[35] >> 4) & 0x07, data[35] & 0x0F);
break;
}
puts ("Manufacturer's JEDEC ID ");
puts ("Manufacturer's Part Number ");
printf("Revision Code %02X %02X\n", data[91], data[92]);
printf("Manufacturing Date %02X %02X\n", data[93], data[94]);
puts ("Assembly Serial Number ");
if (DDR2 != type) {
printf("Speed rating PC%d\n",
data[126] == 0x66 ? 66 : data[126]);
}
#if defined(CONFIG_I2C_CMD_TREE)
#if defined(CONFIG_I2C_MULTI_BUS)
int do_i2c_bus_num(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
int bus_idx, ret=0;
if (argc == 1)
/* querying current setting */
printf("Current bus is %d\n", i2c_get_bus_num());
bus_idx = simple_strtoul(argv[1], NULL, 10);
printf("Setting bus to %d\n", bus_idx);
ret = i2c_set_bus_num(bus_idx);
printf("Failure changing bus number (%d)\n", ret);
}
return ret;
}
#endif /* CONFIG_I2C_MULTI_BUS */
int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
int speed, ret=0;
if (argc == 1)
/* querying current speed */
printf("Current bus speed=%d\n", i2c_get_bus_speed());
speed = simple_strtoul(argv[1], NULL, 10);
printf("Setting bus speed to %d Hz\n", speed);
ret = i2c_set_bus_speed(speed);
printf("Failure changing bus speed (%d)\n", ret);
}
return ret;
}
int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
#if defined(CONFIG_I2C_MULTI_BUS)
return do_i2c_bus_num(cmdtp, flag, --argc, ++argv);
#endif /* CONFIG_I2C_MULTI_BUS */
return do_i2c_bus_speed(cmdtp, flag, --argc, ++argv);
return do_i2c_md(cmdtp, flag, --argc, ++argv);
return do_i2c_mm(cmdtp, flag, --argc, ++argv);
return do_i2c_mw(cmdtp, flag, --argc, ++argv);
return do_i2c_nm(cmdtp, flag, --argc, ++argv);
return do_i2c_crc(cmdtp, flag, --argc, ++argv);
return do_i2c_probe(cmdtp, flag, --argc, ++argv);
return do_i2c_loop(cmdtp, flag, --argc, ++argv);
#if defined(CONFIG_CMD_SDRAM)
return do_sdram(cmdtp, flag, --argc, ++argv);
else
printf ("Usage:\n%s\n", cmdtp->usage);
return 0;
}
#endif /* CONFIG_I2C_CMD_TREE */
/***************************************************/
#if defined(CONFIG_I2C_CMD_TREE)
U_BOOT_CMD(
i2c, 6, 1, do_i2c,
"i2c - I2C sub-system\n",
#if defined(CONFIG_I2C_MULTI_BUS)
"dev [dev] - show or set current I2C bus\n"
#endif /* CONFIG_I2C_MULTI_BUS */
"i2c speed [speed] - show or set I2C bus speed\n"
"i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n"
"i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n"
"i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n"
"i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n"
"i2c crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
"i2c probe - show devices on the I2C bus\n"
"i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device\n"
#if defined(CONFIG_CMD_SDRAM)
"i2c sdram chip - print SDRAM configuration information\n"
);
#endif /* CONFIG_I2C_CMD_TREE */
U_BOOT_CMD(
imd, 4, 1, do_i2c_md, \
"imd - i2c memory display\n", \
"chip address[.0, .1, .2] [# of objects]\n - i2c memory display\n" \
);
U_BOOT_CMD(
imm, 3, 1, do_i2c_mm,
"imm - i2c memory modify (auto-incrementing)\n",
"chip address[.0, .1, .2]\n"
" - memory modify, auto increment address\n"
);
U_BOOT_CMD(
inm, 3, 1, do_i2c_nm,
"inm - memory modify (constant address)\n",
"chip address[.0, .1, .2]\n - memory modify, read and keep address\n"
);
U_BOOT_CMD(
imw, 5, 1, do_i2c_mw,
"imw - memory write (fill)\n",
"chip address[.0, .1, .2] value [count]\n - memory write (fill)\n"
);
U_BOOT_CMD(
icrc32, 5, 1, do_i2c_crc,
"icrc32 - checksum calculation\n",
"chip address[.0, .1, .2] count\n - compute CRC32 checksum\n"
);
U_BOOT_CMD(
iprobe, 1, 1, do_i2c_probe,
"iprobe - probe to discover valid I2C chip addresses\n",
"\n -discover valid I2C chip addresses\n"
);
/*
* Require full name for "iloop" because it is an infinite loop!
*/
U_BOOT_CMD(
iloop, 5, 1, do_i2c_loop,
"iloop - infinite loop on address range\n",
"chip address[.0, .1, .2] [# of objects]\n"
" - loop, reading a set of addresses\n"
);
#if defined(CONFIG_CMD_SDRAM)
U_BOOT_CMD(
isdram, 2, 1, do_sdram,
"isdram - print SDRAM configuration information\n",
"chip\n - print SDRAM configuration information\n"
" (valid chip values 50..57)\n"
);
#endif