partner: add platforms and targets for aller, tagus and nereid boards

partner: add fomu target

This adds the Fomu target back in.  The default BaseSoC supports
various USB methods, and will be updated as more become available.

The debug bridge may optionally be added.

Signed-off-by: Sean Cross <sean@xobs.io>

targets/__init__: comment targets import until we found a way to avoid litedram/liteeth dependecies for targets no using them.

Fix ecp5_evn clock

The system clock was driven directly while it should be driven by the PLL.

Turn litex_boards.community into module

Add ECP5 Evaluation Board

Exact PLL clock can be derived from U1 12 Mhz or X5 50 Mhz clock.

- use 1e9/freq for default_clk_period
- add default serial on tinyfpga_bx
- use S6PLL on minispartan6
- add SPIFlash pins on versa_ecp5

community: Add TrellisBoard

Signed-off-by: David Shah <dave@ds0.me>

Turn litex_boards.partner into module

Add litex_boards package to setup.py