Leads to an increase in DP16KD, first noticed in
https://github.com/enjoy-digital/liteeth/issues/70.
With full_mem_we:
```
Info: 	              DP16KD:    41/   56    73%
```
Without:
```
Info: 	              DP16KD:    29/   56    51%
```

trenz_tec0117: Add SDCard (SPI and SD mode), move SPI Flash to 0x00000000 and use default l2_cache_min_data_width.

Signed-off-by: Tim Callahan <tcal@google.com>

trenz_tec0117: Get BIOS XiP from SPI Flash working, remove CPU variant force since can now fit default VexRiscv config.

trenz_tec0117: Avoid forcing CPU type (only force to lite variant when VexRiscv is selected=default).

Otherwise break retro-compat on external design importing CRG without passing this new parameter.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

LitePCIe Gen3 X4 enumerating correctly.

Most basic SoC ever but ... it runs

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

The pin outs come from LUNA :
https://github.com/greatscottgadgets/luna/blob/main/luna/gateware/platform/icebreaker.py#L94



and are some commonly used ones from other projects / pmods.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

As with the other versions, the clk pin can't be directly driven