Add Mimas A7 board support

aller/tagus/nereid: use crossover UART, rename SoC to PCIe SoC and pass soc_sdram_argdict to PCIeSoC

ADD: KX2 and DDR3 support

targets/de10lite: use external clock for sys directly

At the start output of the pll is not stabilized, which
caused malfunctions when used for sys clock domain.
Use AsyncResetSynchronizer to start clock domains
on pll locked signal.