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Commit 908539d4 authored by Florent Kermarrec's avatar Florent Kermarrec
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targets/nexys4ddr: fix typo

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litex_boards/official/targets/nexys4ddr.py
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......@@ -79,7 +79,7 @@ class EthernetSoC(BaseSoC):
# Ethernet ---------------------------------------------------------------------------------
# phy
self.submodules.ethphy = LiteEthPHYMII(
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
......
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