targets/nexys_video: Revert clk100 to avoid breaking Linux-on-LiteX-VexRiscv (we'll remove it when the switch the simple framebuffer will be done).

alveo_u280: Fix copyrights (avoid too much cascading on Platforms/Targets) and generate reset on idelay clock domain (similarly to recent change on others Ultrascale+ boards).

Alveo U280 board

crosslink_nx_vip: Remove constraints for hard MIPI pins

arty: Add an option to enable jtagbone

targets/versa_ecp5: Fix LiteEthPHYRMGII tx/rx delays (need to be updated due to a bug fix in the ECP5RGMII PHY).

Signed-off-by: gatecat <gatecat@ds0.me>

Then adds jtagbone for arty.  I have tested with the following
litex_server and it seems to work fine.

  litex_server --jtag --jtag-config openocd_xc7_ft2232.cfg

Note, the jtagbone and etherbone may be mutually exclusive, but I am not
sure how to define that in the args.

crosslink_nx_vip: Camera IO fixes

Signed-off-by: gatecat <gatecat@ds0.me>

Signed-off-by: gatecat <gatecat@ds0.me>

targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence).

Tested with: ./icebreaker.py --cpu-type=serv --with-video-terminal --build --flash

https://twitter.com/enjoy_digital/status/1365324823447171074

README.md: fix typo

Numato sdcard pmod for Arty

Add board support for Terasic/Arrow DECA board (Intel Max10)

target/arty: add eth_ip_configurable switch

The default stays with the Digilent/Antmicro layout, but the user can
optionally provide --sdcard-adaptor numato to use the Numato layout.

Signed-off-by: Joel Stanley <joel@jms.id.au>

It has a different layout.

Thanks to David for documenting the pinout in this issue:
https://github.com/enjoy-digital/litex/issues/817



 Expansion Pin 	SD 	SPI SD 	Artix 	Arty-A7 	PMOD PIN 	PMOD Index
 2 		DATA_2 	  	D4 	JD1 		1 		0
 4 		CMD 	MOSI 	D3 	JD2 		2 		1
 6 		DATA_0 	MISO 	F4 	JD3 		3 		2
   		CD 	  	F3 	JD4 		4 		3
 1 		DATA_3 	CS_N 	E2 	JD7 		7 		4
 3 		CLK 	CLK 	D2 	JD8 		8 		5
 5 		DATA_1 	  	H2 	JD9 		9 		6
   	  		  	G2 	JD10

Signed-off-by: Joel Stanley <joel@jms.id.au>

fix vc707 default_clk_period