trenz_tec0117: Get BIOS XiP from SPI Flash working, remove CPU variant force since can now fit default VexRiscv config.

trenz_tec0117: Avoid forcing CPU type (only force to lite variant when VexRiscv is selected=default).

Otherwise break retro-compat on external design importing CRG without passing this new parameter.

setup.py: Exclude test package

icebreaker: Minor fix to usb (add PMOD2 position and fix typo)

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

LitePCIe Gen3 X4 enumerating correctly.

Misc improvements for the icebreaker family of boards

Most basic SoC ever but ... it runs

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

The pin outs come from LUNA :
https://github.com/greatscottgadgets/luna/blob/main/luna/gateware/platform/icebreaker.py#L94



and are some commonly used ones from other projects / pmods.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

Fix colorlight 5a 75b v6.1 flash pins

As with the other versions, the clk pin can't be directly driven

QMTech EP4CE15: Add daughterboard support, small DECA addition

Add digilent basys3 board support

CYC1000: Add initial support of CYC1000 board