- Sep 20, 2021
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Florent Kermarrec authored
With colorbars for now, need to free up BRAMS for Video Terminal (or finish HyperRAM support).
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- Sep 17, 2021
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Florent Kermarrec authored
sipeed_tang_nano: Add SPI Flash, Enable CPU and use new external SPI Flash support from OpenFPGALoader. ./sipeed_tang_nano_4k.py --cpu-type=vexriscv --cpu-variant=lite --build --flash __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Build your hardware, easily! (c) Copyright 2012-2021 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on Sep 17 2021 15:54:08 BIOS CRC passed (6cc6de6d) Migen git sha1: a5bc262 LiteX git sha1: 46cd9c5a --=============== SoC ==================-- CPU: VexRiscv_Lite @ 27MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 64KiB SRAM: 8KiB FLASH: 4096KiB --========== Initialization ============-- Initializing W25Q32 SPI Flash @0x80000000... SPI Flash clk configured to 13 MHz Memspeed at 0x80000000 (Sequential, 4.0KiB)... Read speed: 1.3MiB/s Memspeed at 0x80000000 (Random, 4.0KiB)... Read speed: 521.9KiB/s --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro Timeout No boot medium found --============= Console ================-- litex>
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- Sep 16, 2021
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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- Sep 15, 2021
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Gwenhael Goavec-Merou authored
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Gwenhael Goavec-Merou authored
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- Sep 10, 2021
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Nathaniel R. Lewis authored
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- Sep 09, 2021
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Gwenhael Goavec-Merou authored
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Florent Kermarrec authored
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Nathaniel R. Lewis authored
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- Sep 08, 2021
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
./sispeed_tang_nano_4k.py --build --load Build with Gowin EDA. Load with OpenFPGALoader.
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- Sep 02, 2021
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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- Sep 01, 2021
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Florent Kermarrec authored
Validated with: ./gsd_butterstick.py --uart-name=crossover --with-etherbone --csr-csv=csr.csv --build --load litex_server --udp litex_term bridge __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Build your hardware, easily! (c) Copyright 2012-2021 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on Sep 1 2021 19:09:52 BIOS CRC passed (3d349845) Migen git sha1: 27dbf03 LiteX git sha1: 315fbe18 --=============== SoC ==================-- CPU: VexRiscv @ 75MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 128KiB SRAM: 8KiB L2: 8KiB SDRAM: 524288KiB 16-bit @ 300MT/s (CL-6 CWL-5) --========== Initialization ============-- Initializing SDRAM @0x40000000... Switching SDRAM to software control. Read leveling: m0, b00: |01110000| delays: 02+-01 m0, b01: |00000000| delays: - m0, b02: |00000000| delays: - m0, b03: |00000000| delays: - best: m0, b00 delays: 02+-01 m1, b00: |01110000| delays: 02+-01 m1, b01: |00000000| delays: - m1, b02: |00000000| delays: - m1, b03: |00000000| delays: - best: m1, b00 delays: 02+-01 Switching SDRAM to hardware control. Memtest at 0x40000000 (2.0MiB)... Write: 0x40000000-0x40200000 2.0MiB Read: 0x40000000-0x40200000 2.0MiB Memtest OK Memspeed at 0x40000000 (Sequential, 2.0MiB)... Write speed: 13.6MiB/s Read speed: 15.6MiB/s --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro Timeout No boot medium found --============= Console ================-- litex>
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
- Now uses regular UART. - Build tested with: ./quertyembedded_beaglewire.py --cpu-type=serv --build - Can still be build with Crossover UART with --uart-name=crossover+bridge.
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Florent Kermarrec authored
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Florent Kermarrec authored
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- Aug 31, 2021
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Dhiru Kholia authored
Usage: ``` ./ebaz4205.py --cpu-type=vexriscv --build --load ``` ``` $ pwd litex-boards/litex_boards/targets ``` Tip: Use `GTKTerm` to connect to /dev/ttyUSB0 (usually) and interact with the LiteX BIOS. References: - https://github.com/fusesoc/blinky#ebaz4205-development-board - https://github.com/olofk/serv/#ebaz4205-development-board - https://github.com/xjtuecho/EBAZ4205#ebaz4205 - https://github.com/nmigen/nmigen-boards/pull/180 (merged) - https://github.com/olofk/corescore/pull/33 - The existing 'Zybo Z7' example Note: The `PS7` stuff remains untested via LiteX for now.
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- Aug 30, 2021
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Yoshimasa Niwa authored
**Problems** `SPIMaster` pad names are `clk`, `cs_n`, `mosi`, and `miso`. However, `feather_spi` is using `sck` instead of `clk`, therefore it is not able to use as-is for `SPIMaster`, for example, with `add_spi` on Linux On LiteX VexRiscv. **Solution** In fact, `spisdcard` and other SPI related pad names are using `clk`, only `feather_spi` is using `sck`. Therefore, rename `sck` to `clk`.
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- Aug 17, 2021
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Dan Callaghan authored
This board is documented as having the LIFCL-40-9BG400C part, but some versions of the board exist which were fitted with LIFCL-40-8BG400CES, an engineering sample part. The distinction is important because the engineering sample requires a different device ID to be embedded in the bitstream. If you try to build a bitstream for LIFCL-40-9BG400C and load it onto LIFCL-40-8BG400CES the configuration fails (indicated by the red "INITN" LED on this board). Accept --device to allow the user to specify which FPGA part their board has.
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- Aug 16, 2021
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ombhilare999 authored
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- Aug 13, 2021
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Martin Troiber authored
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- Jul 28, 2021
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Sergiu Mosanu authored
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Florent Kermarrec authored
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- Jul 27, 2021
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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- Jul 22, 2021
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Lucas Teske authored
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- Jul 21, 2021
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Florent Kermarrec authored
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