With colorbars for now, need to free up BRAMS for Video Terminal (or finish HyperRAM support).

sipeed_tang_nano: Add SPI Flash, Enable CPU and use new external SPI Flash support from OpenFPGALoader.

./sipeed_tang_nano_4k.py --cpu-type=vexriscv --cpu-variant=lite --build --flash

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2021 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Sep 17 2021 15:54:08
 BIOS CRC passed (6cc6de6d)

 Migen git sha1: a5bc262
 LiteX git sha1: 46cd9c5a

--=============== SoC ==================--
CPU:		VexRiscv_Lite @ 27MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		64KiB
SRAM:		8KiB
FLASH:		4096KiB

--========== Initialization ============--

Initializing W25Q32 SPI Flash @0x80000000...
SPI Flash clk configured to 13 MHz
Memspeed at 0x80000000 (Sequential, 4.0KiB)...
   Read speed: 1.3MiB/s
Memspeed at 0x80000000 (Random, 4.0KiB)...
   Read speed: 521.9KiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>

./sispeed_tang_nano_4k.py --build --load

Build with Gowin EDA.
Load with OpenFPGALoader.

arty: Switch SPI Flash rate to 1:2 (DDR) (Possible on Arty since SPI Flash's clk does not require use of STARTUPE2).

On the Digilent Arty, the SPI Flash's clk is connected to CCLK (that can be driven
through the STARTUPE2) but also to another generic IO that can be use to drive the
clock through DDR primitives.

Validated with:
./gsd_butterstick.py --uart-name=crossover --with-etherbone --csr-csv=csr.csv --build --load
litex_server --udp
litex_term bridge


        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2021 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Sep  1 2021 19:09:52
 BIOS CRC passed (3d349845)

 Migen git sha1: 27dbf03
 LiteX git sha1: 315fbe18

--=============== SoC ==================--
CPU:		VexRiscv @ 75MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		128KiB
SRAM:		8KiB
L2:		8KiB
SDRAM:		524288KiB 16-bit @ 300MT/s (CL-6 CWL-5)

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Read leveling:
  m0, b00: |01110000| delays: 02+-01
  m0, b01: |00000000| delays: -
  m0, b02: |00000000| delays: -
  m0, b03: |00000000| delays: -
  best: m0, b00 delays: 02+-01
  m1, b00: |01110000| delays: 02+-01
  m1, b01: |00000000| delays: -
  m1, b02: |00000000| delays: -
  m1, b03: |00000000| delays: -
  best: m1, b00 delays: 02+-01
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40200000 2.0MiB
   Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
  Write speed: 13.6MiB/s
   Read speed: 15.6MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>

Setting MASTER_SPI_PORT=SERIAL causes the SPI flash pins to be reserved
for use by the sysCONFIG logic, and prevents user logic from assigning
them. This made it impossible to have a Litex design which accesses the
SPI flash on this board.

Remove the setting, so that we get the default behaviour which permits
user logic to assign these pins. In the unlikely event that someone
needs the pins to stay reserved for sysCONFIG after configuration (I'm
not sure why this would be needed) they could explicitly add this
command in their design.

- Now uses regular UART.
- Build tested with: ./quertyembedded_beaglewire.py --cpu-type=serv --build
- Can still be build with Crossover UART with --uart-name=crossover+bridge.

ebaz4205: Remove PS7 support for now (since untested and we'll avoid the .xci in LiteX-Boards repository).

Usage:

```
./ebaz4205.py --cpu-type=vexriscv --build --load
```

```
$ pwd
litex-boards/litex_boards/targets
```

Tip: Use `GTKTerm` to connect to /dev/ttyUSB0 (usually) and interact
with the LiteX BIOS.

References:

- https://github.com/fusesoc/blinky#ebaz4205-development-board
- https://github.com/olofk/serv/#ebaz4205-development-board
- https://github.com/xjtuecho/EBAZ4205#ebaz4205
- https://github.com/nmigen/nmigen-boards/pull/180 (merged)
- https://github.com/olofk/corescore/pull/33
- The existing 'Zybo Z7' example

Note: The `PS7` stuff remains untested via LiteX for now.

**Problems**

`SPIMaster` pad names are `clk`, `cs_n`, `mosi`, and `miso`.
However, `feather_spi` is using `sck` instead of `clk`, therefore
it is not able to use as-is for `SPIMaster`, for example,
with `add_spi` on Linux On LiteX VexRiscv.

**Solution**

In fact, `spisdcard` and other SPI related pad names are
using `clk`, only `feather_spi` is using `sck`.
Therefore, rename `sck` to `clk`.