Keep the old add_spi_flash call commented for now just in case we need to compare/test it.

Already better regarding resource usage:
Info: 	         ICESTORM_LC:  2938/ 5280    55%
Info: 	        ICESTORM_RAM:     2/   30     6%
Info: 	               SB_IO:    15/   96    15%
Info: 	               SB_GB:     8/    8   100%
Info: 	        ICESTORM_PLL:     1/    1   100%
Info: 	         SB_WARMBOOT:     0/    1     0%
Info: 	        ICESTORM_DSP:     0/    8     0%
Info: 	      ICESTORM_HFOSC:     0/    1     0%
Info: 	      ICESTORM_LFOSC:     0/    1     0%
Info: 	              SB_I2C:     0/    2     0%
Info: 	              SB_SPI:     0/    2     0%
Info: 	              IO_I3C:     0/    2     0%
Info: 	         SB_LEDDA_IP:     0/    1     0%
Info: 	         SB_RGBA_DRV:     0/    1     0%
Info: 	      ICESTORM_SPRAM:     4/    4   100%

Requires https://github.com/enjoy-digital/litex/commit/80e9d2cea9198b38f62a68bc420328222b3b6709

Already better regarding resource usage:

Info: 	         ICESTORM_LC:  2358/ 5280    44%
Info: 	        ICESTORM_RAM:     2/   30     6%
Info: 	               SB_IO:    15/   96    15%
Info: 	               SB_GB:     8/    8   100%
Info: 	        ICESTORM_PLL:     1/    1   100%
Info: 	         SB_WARMBOOT:     0/    1     0%
Info: 	        ICESTORM_DSP:     0/    8     0%
Info: 	      ICESTORM_HFOSC:     0/    1     0%
Info: 	      ICESTORM_LFOSC:     0/    1     0%
Info: 	              SB_I2C:     0/    2     0%
Info: 	              SB_SPI:     0/    2     0%
Info: 	              IO_I3C:     0/    2     0%
Info: 	         SB_LEDDA_IP:     0/    1     0%
Info: 	         SB_RGBA_DRV:     0/    1     0%
Info: 	      ICESTORM_SPRAM:     4/    4   100%

We can still try to reduce it, but enabling Master should not use that much LCs.

Both XiP from SPI(1X) or QSPI(4X) are working, but resource usage is currently
too high to be able to switch to it by default. We'll first try to reduce it.

Resource usage using SPI(1X) and actual LiteX SPI Flash core:
Info: Device utilisation:
Info: 	         ICESTORM_LC:  2016/ 5280    38%
Info: 	        ICESTORM_RAM:     2/   30     6%
Info: 	               SB_IO:    15/   96    15%
Info: 	               SB_GB:     8/    8   100%
Info: 	        ICESTORM_PLL:     1/    1   100%
Info: 	         SB_WARMBOOT:     0/    1     0%
Info: 	        ICESTORM_DSP:     0/    8     0%
Info: 	      ICESTORM_HFOSC:     0/    1     0%
Info: 	      ICESTORM_LFOSC:     0/    1     0%
Info: 	              SB_I2C:     0/    2     0%
Info: 	              SB_SPI:     0/    2     0%
Info: 	              IO_I3C:     0/    2     0%
Info: 	         SB_LEDDA_IP:     0/    1     0%
Info: 	         SB_RGBA_DRV:     0/    1     0%
Info: 	      ICESTORM_SPRAM:     4/    4   100%


Resource usage using LiteSPI:
Info: Device utilisation:
Info: 	         ICESTORM_LC:  3964/ 5280    75%
Info: 	        ICESTORM_RAM:     2/   30     6%
Info: 	               SB_IO:    15/   96    15%
Info: 	               SB_GB:     8/    8   100%
Info: 	        ICESTORM_PLL:     1/    1   100%
Info: 	         SB_WARMBOOT:     0/    1     0%
Info: 	        ICESTORM_DSP:     0/    8     0%
Info: 	      ICESTORM_HFOSC:     0/    1     0%
Info: 	      ICESTORM_LFOSC:     0/    1     0%
Info: 	              SB_I2C:     0/    2     0%
Info: 	              SB_SPI:     0/    2     0%
Info: 	              IO_I3C:     0/    2     0%
Info: 	         SB_LEDDA_IP:     0/    1     0%
Info: 	         SB_RGBA_DRV:     0/    1     0%
Info: 	      ICESTORM_SPRAM:     4/    4   100%

trenz_tec0117: Add SDCard (SPI and SD mode), move SPI Flash to 0x00000000 and use default l2_cache_min_data_width.

1.  Digilent CMOD A7
      https://reference.digilentinc.com/programmable-logic/cmod-a7/start

2. Digilent Nexys 4
      https://reference.digilentinc.com/programmable-logic/nexys-4/start

3. MicroNova Mercury 2
      https://www.micro-nova.com/mercury-2

Signed-off-by: Tim Callahan <tcal@google.com>

trenz_tec0117: Get BIOS XiP from SPI Flash working, remove CPU variant force since can now fit default VexRiscv config.

trenz_tec0117: Avoid forcing CPU type (only force to lite variant when VexRiscv is selected=default).

Otherwise break retro-compat on external design importing CRG without passing this new parameter.

LitePCIe Gen3 X4 enumerating correctly.

Most basic SoC ever but ... it runs

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>