diff --git a/litex_boards/official/targets/nexys4ddr.py b/litex_boards/official/targets/nexys4ddr.py
index 14a469af5b8cc2787e857dd330c6df4938dab71c..3796bb485af72f5c6bb37ce103f19e8fd3ebd8c7 100755
--- a/litex_boards/official/targets/nexys4ddr.py
+++ b/litex_boards/official/targets/nexys4ddr.py
@@ -79,7 +79,7 @@ class EthernetSoC(BaseSoC):
 
         # Ethernet ---------------------------------------------------------------------------------
         # phy
-        self.submodules.ethphy = LiteEthPHYMII(
+        self.submodules.ethphy = LiteEthPHYRMII(
             clock_pads = self.platform.request("eth_clocks"),
             pads       = self.platform.request("eth"))
         self.add_csr("ethphy")