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  • reform/reform-boundary-uboot
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with 2490 additions and 1380 deletions
.gitlab-ci.yml 0 → 100644
View file @ 8e809399
image: debian:bullseye-slim
build:
script: |
apt-get update
apt-get --yes install --no-install-recommends gcc-aarch64-linux-gnu build-essential bison flex device-tree-compiler git
cp mntreform-config .config
./build.sh
if git describe >/dev/null 2>&1; then
grep --quiet --fixed-strings "EXTRAVERSION = \\ MNT\\ Reform\\ $(git describe --always --tags --abbrev=0)" Makefile
fi
mv flash.bin imx8mq-mnt-reform2-flash.bin
cp imx8mq-mnt-reform2-flash.bin imx8mq-mnt-reform2-hdmi-flash.bin
artifacts:
paths:
- "imx8mq-mnt-reform2-flash.bin"
- "imx8mq-mnt-reform2-hdmi-flash.bin"
Makefile
View file @ 8e809399
......@@ -3,7 +3,7 @@
VERSION = 2018
PATCHLEVEL = 07
SUBLEVEL =
EXTRAVERSION =
EXTRAVERSION = \ MNT\ Reform\ 2024-07-19
NAME =
# *DOCUMENTATION*
......@@ -607,14 +607,18 @@ endif
KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector)
KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks)
# change __FILE__ to the relative path from the srctree
KBUILD_CFLAGS += $(call cc-option,-fmacro-prefix-map=$(srctree)/=)
# change __FILE__ and debugging symbols to the relative path from the
# srctree
KBUILD_CFLAGS += $(call cc-option,-ffile-prefix-map=$(srctree)/=)
KBUILD_CFLAGS += -g
# $(KBUILD_AFLAGS) sets -g, which causes gcc to pass a suitable -g<format>
# option to the assembler.
KBUILD_AFLAGS += -g
# Use relative paths in debugging symbols
KBUILD_AFLAGS += --debug-prefix-map=$(srctree)/=
# Report stack usage if supported
# ARC tools based on GCC 7.1 has an issue with stack usage
# with naked functions, see commit message for more details
......@@ -1077,7 +1081,7 @@ endif
ifdef CONFIG_IMX8MN
SOC_CPU = iMX8MN
TEE_LOAD_ADDR = 0xbe000000
ATF_LOAD_ADDR = 0x00920000
ATF_LOAD_ADDR = 0x00960000
endif
ifdef CONFIG_IMX8MQ
SOC_CPU = iMX8MQ
......
arch/arm/dts/imx8mq-nitrogen8m_som.dts
View file @ 8e809399
......@@ -310,13 +310,6 @@
>;
};
pinctrl_reg_wlan_vmmc: reg-wlan-vmmcgrp {
fsl,pins = <
#define GP_REG_WLAN_VMMC <&gpio3 20 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x16
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
/* wm8960 */
......@@ -406,12 +399,6 @@
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
#if 0
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
#else
#define GP_EMMC_RESET <&gpio2 10 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
#endif
>;
};
......@@ -445,6 +432,7 @@
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x03
......@@ -453,8 +441,6 @@
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
/* Bluetooth slow clock */
MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x03
>;
};
......@@ -603,18 +589,6 @@
regulator-max-microvolt = <5000000>;
};
reg_wlan_vmmc: regulator-wlan-vmmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_wlan_vmmc>;
regulator-name = "reg_wlan_vmmc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = GP_REG_WLAN_VMMC;
startup-delay-us = <70000>;
enable-active-high;
};
#if 0
sound-wm8960 {
compatible = "fsl,imx-audio-wm8960";
......@@ -1332,8 +1306,8 @@
&usdhc1 {
cap-mmc-highspeed;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
// mmc-ddr-1_8v;
// mmc-hs200-1_8v;
fsl,strobe-dll-delay-target = <5>;
fsl,tuning-start-tap = <63>;
fsl,tuning-step = <2>;
......@@ -1348,7 +1322,6 @@
vqmmc-1-8-v;
};
#if 0
&usdhc2 {
bus-width = <4>;
fsl,tuning-start-tap = <70>;
......@@ -1362,15 +1335,9 @@
status = "okay";
tuning-delay = <32>;
tuning-mode = <1>;
vmmc-supply = <&reg_wlan_vmmc>;
vqmmc-1-8-v;
vmmc-supply = <&reg_vref_3v3>;
};
&vpu {
regulator-supply = <&reg_vref_0v9>;
status = "okay";
};
#endif
&wdog1 {
pinctrl-names = "default";
......
arch/arm/mach-imx/imx8m/clock_imx8mq.c
View file @ 8e809399
......@@ -924,3 +924,55 @@ U_BOOT_CMD(
""
);
#endif
int mx8mq_showclocks() {
u32 freq;
freq = decode_frac_pll(ARM_PLL_CLK);
printf("ARM_PLL %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL1_800M_CLK);
printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL1_400M_CLK);
printf("SYS_PLL1_400 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL1_266M_CLK);
printf("SYS_PLL1_266 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL1_200M_CLK);
printf("SYS_PLL1_200 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL1_160M_CLK);
printf("SYS_PLL1_160 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL1_133M_CLK);
printf("SYS_PLL1_133 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL1_100M_CLK);
printf("SYS_PLL1_100 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL1_80M_CLK);
printf("SYS_PLL1_80 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL1_40M_CLK);
printf("SYS_PLL1_40 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL2_1000M_CLK);
printf("SYS_PLL2_1000 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL2_500M_CLK);
printf("SYS_PLL2_500 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL2_333M_CLK);
printf("SYS_PLL2_333 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL2_250M_CLK);
printf("SYS_PLL2_250 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL2_200M_CLK);
printf("SYS_PLL2_200 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL2_166M_CLK);
printf("SYS_PLL2_166 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL2_125M_CLK);
printf("SYS_PLL2_125 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL2_100M_CLK);
printf("SYS_PLL2_100 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL2_50M_CLK);
printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL3_CLK);
printf("SYS_PLL3 %8d MHz\n", freq / 1000000);
freq = mxc_get_clock(UART1_CLK_ROOT);
printf("UART1 %8d MHz\n", freq / 1000000);
freq = mxc_get_clock(USDHC1_CLK_ROOT);
printf("USDHC1 %8d MHz\n", freq / 1000000);
freq = mxc_get_clock(QSPI_CLK_ROOT);
printf("QSPI %8d MHz\n", freq / 1000000);
return 0;
}
arch/arm/mach-imx/imx8m/imximage.cfg
View file @ 8e809399
......@@ -7,9 +7,7 @@
FIT
BOOT_FROM sd
#ifdef CONFIG_IMX8MQ
SIGNED_HDMI signed_hdmi_imx8m.bin
#endif
LOADER spl/u-boot-spl-ddr.bin 0x7E1000
SECOND_LOADER u-boot.itb 0x40200000 0x60000
......
arch/arm/mach-imx/imx8m/soc.c
View file @ 8e809399
......@@ -203,8 +203,8 @@ u32 get_cpu_rev(void)
rom_version =
readl((void __iomem *)ROM_VERSION_A0);
if (rom_version != CHIP_REV_1_0) {
rom_version = readl((void __iomem *)ROM_VERSION_B0);
if (rom_version == CHIP_REV_2_0)
rom_version = readl((void __iomem *)ROM_VERSION_B0) & 0xff;
if (rom_version >= CHIP_REV_2_0)
reg = CHIP_REV_2_0;
}
}
......
board/boundary/common/bd_common.c
View file @ 8e809399
......@@ -64,9 +64,8 @@ int board_mmc_getcd(struct mmc *mmc)
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int gp_cd = cfg->gp_cd;
if (!gp_cd)
return 1; /* eMMC always present */
return !gpio_get_value(gp_cd);
// force SD/MMC presence
return 1;
}
#if defined(CONFIG_MX51)
......@@ -86,7 +85,8 @@ int board_mmc_init(bd_t *bis)
int ret;
u32 index = 0;
for (index = 0; index < CNT; index++) {
// init both controllers
for (index = 0; index < 2; index++) {
struct fsl_esdhc_cfg *cfg = &board_usdhc_cfg[index];
if (cfg->esdhc_base == BASE1) {
......
board/boundary/common/mx6/800mhz_256mx16.cfg
View file @ 8e809399
......@@ -56,14 +56,14 @@
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
/*
* tRFC:0x66 (260000/2525) = 102.97 = 103(0x67) clocks
* tRFC:0x69 (267000/2525) = 105.74 = 106(0x6a) clocks
* tXS:0x6a (270000/2525) = 106.93 = 107(0x6b) clocks
* tXP:b'010' (6000/2525) = 2.376 = 3 clocks
* tXPDLL:b'1001' (24000/2525) = 9.505 = 10(0x0a) clocks
* tFAW:b'10011' (50000/2525) = 19.802 = 20(0x14) clocks
* tCL:b'0011' (13125/2525) = 5.198 = 6 clocks
*/
DATA 4, MX6_MMDC_P0_MDCFG0, 0x666a5333
DATA 4, MX6_MMDC_P0_MDCFG0, 0x696a5333
/*
* tRCD:b'101' (13125/2525) = 5.198 = 6 clocks
* tRP:b'101' (13125/2525) = 5.198 = 6 clocks
......
board/boundary/nitrogen8m_som/Kconfig
View file @ 8e809399
......@@ -9,6 +9,18 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "nitrogen8m_som"
config DDR_RANK_BITS
int "ddr rank bits"
default 1
config DDR_CHANNEL_CNT
int "ddr channel cnt"
default 2
config DDR_DRIVE_STRENGTH
int "ddr drive strength"
default 6
source "board/boundary/common/Kconfig"
endif
board/boundary/nitrogen8m_som/Makefile
View file @ 8e809399
......@@ -4,9 +4,9 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += nitrogen8m_som.o mmc.o
obj-y += nitrogen8m_som.o mmc.o lcdif.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-y += lpddr4_timing.o
obj-y += lpddr4_timing_8mq.o
endif
board/boundary/nitrogen8m_som/lcdif.c 0 → 100644
View file @ 8e809399
This diff is collapsed.
board/boundary/nitrogen8m_som/lpddr4_timing.c deleted 100644 → 0
View file @ 5e63b20a
This diff is collapsed.
board/boundary/nitrogen8m_som/lpddr4_timing_8mq.c 0 → 100644
View file @ 8e809399
This diff is collapsed.
board/boundary/nitrogen8m_som/lpddr4_timing_ch2.h 0 → 100644
View file @ 8e809399
/*
* Copyright Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <linux/kernel.h>
#include <asm/arch/ddr.h>
#include <asm/arch/lpddr4_define.h>
#include <asm/arch/imx8m_ddr.h>
#ifdef WR_POST_EXT_3200
#define CH2_VAL_INIT4 ((LPDDR4_MR3 << 16) | 0x00020008)
#else
#define CH2_VAL_INIT4 ((LPDDR4_MR3 << 16) | 8)
#endif
#if CONFIG_DDR_MB == 1024
/* Address map is from MSB 28: r14, r13-r0, b2-b0, c9-c0 */
#define CH2_VAL_DDRC_ADDRMAP0_R0 0x0000001F
#define CH2_VAL_DDRC_ADDRMAP6_R0 0x0F070707
#elif CONFIG_DDR_MB == 2048
/* Address map is from MSB 28: r15, r14, r13-r0, b2-b0, c9-c0 */
#define CH2_VAL_DDRC_ADDRMAP0_R0 0x0000001F
#define CH2_VAL_DDRC_ADDRMAP6_R0 0x07070707
/* Address map is from MSB 28: cs, r14, r13-r0, b2-b0, c9-c0 */
#define CH2_VAL_DDRC_ADDRMAP0_R1 0x00000016
#define CH2_VAL_DDRC_ADDRMAP6_R1 0x0F070707
#elif CONFIG_DDR_MB == 3072
/* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
#define CH2_VAL_DDRC_ADDRMAP0_R1 0x00000015
#define CH2_VAL_DDRC_ADDRMAP6_R1 0x48080707
#elif CONFIG_DDR_MB == 4096
/* Address map is from MSB 29: cs, r15, r14, r13-r0, b2-b0, c9-c0 */
#define CH2_VAL_DDRC_ADDRMAP0_R1 0x00000017
#define CH2_VAL_DDRC_ADDRMAP6_R1 0x07070707
#elif CONFIG_DDR_MB == 8192
/* Address map is from MSB 29: cs, r15, r14, r13-r0, b2-b0, c9-c0 */
#define CH2_VAL_DDRC_ADDRMAP0_R1 0x00000018
#define CH2_VAL_DDRC_ADDRMAP6_R1 0x07070707
#else
#error unsupported memory size
#endif
#define LPDDR4_CS_R0 0x1 /* 0 rank bits, 1 chip select */
#define LPDDR4_CS_R1 0x3 /* 1 rank bit, 2 chip selects */
#if (CONFIG_DDR_RANK_BITS == 0) || !defined(CH2_VAL_DDRC_ADDRMAP0_R1)
#ifdef CH2_VAL_DDRC_ADDRMAP0_R0
#define CH2_LPDDR4_CS LPDDR4_CS_R0
#define CH2_VAL_DDRC_ADDRMAP0 CH2_VAL_DDRC_ADDRMAP0_R0
#define CH2_VAL_DDRC_ADDRMAP6 CH2_VAL_DDRC_ADDRMAP6_R0
#else
#error unsupported memory rank/size
#endif
/*
* rank0 will succeed, even if really rank 1, so we need
* to probe memory if rank0 succeeds
*/
#if defined(CH2_VAL_DDRC_ADDRMAP0_R0) && defined(CH2_VAL_DDRC_ADDRMAP0_R1)
#define CH2_LPDDR4_CS_NEW LPDDR4_CS_R1
#define CH2_VAL_DDRC_ADDRMAP0_NEW CH2_VAL_DDRC_ADDRMAP0_R1
#define CH2_VAL_DDRC_ADDRMAP6_NEW CH2_VAL_DDRC_ADDRMAP6_R1
#endif
#elif (CONFIG_DDR_RANK_BITS == 1) || !defined(CH2_VAL_DDRC_ADDRMAP0_R0)
#ifdef CH2_VAL_DDRC_ADDRMAP0_R1
#define CH2_LPDDR4_CS LPDDR4_CS_R1
#define CH2_VAL_DDRC_ADDRMAP0 CH2_VAL_DDRC_ADDRMAP0_R1
#define CH2_VAL_DDRC_ADDRMAP6 CH2_VAL_DDRC_ADDRMAP6_R1
#else
#error unsupported memory rank/size
#endif
#if defined(CH2_VAL_DDRC_ADDRMAP0_R0) && defined(CH2_VAL_DDRC_ADDRMAP0_R1)
#define CH2_LPDDR4_CS_NEW LPDDR4_CS_R0
#define CH2_VAL_DDRC_ADDRMAP0_NEW CH2_VAL_DDRC_ADDRMAP0_R0
#define CH2_VAL_DDRC_ADDRMAP6_NEW CH2_VAL_DDRC_ADDRMAP6_R0
#endif
#else
#error unsupported rank bits
#endif
#if (CONFIG_DDR_CHANNEL_CNT == 2)
#if (CONFIG_DDR_RANK_BITS == 0) && !defined(CH2_VAL_DDRC_ADDRMAP0_R0)
#error unsupported options
#endif
#if (CONFIG_DDR_RANK_BITS == 1) && !defined(CH2_VAL_DDRC_ADDRMAP0_R1)
#error unsupported options
#endif
#endif
board/boundary/nitrogen8m_som/nitrogen8m_som.c
View file @ 8e809399
......@@ -41,11 +41,10 @@ static iomux_v3_cfg_t const init_pads[] = {
IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
#define GP_LCM_JM430_BKL_EN IMX_GPIO_NR(1, 1)
/* This enables 5V power on LTK080A60A004T mipi display */
#define GP_LTK08_MIPI_EN IMX_GPIO_NR(1, 1)
IMX8MQ_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(0x16),
#define GPIRQ_GT911 IMX_GPIO_NR(3, 12)
#define GPIRQ_GT911 IMX_GPIO_NR(3, 12)
IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12 | MUX_PAD_CTRL(0xd6),
#define GP_GT911_RESET IMX_GPIO_NR(3, 13)
#define GP_ST1633_RESET IMX_GPIO_NR(3, 13)
......@@ -83,7 +82,6 @@ static iomux_v3_cfg_t const init_pads[] = {
#define GP_CSI2_MIPI_RESET IMX_GPIO_NR(2, 19)
IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 |MUX_PAD_CTRL(0x61),
#ifdef CONFIG_FEC_MXC
/* PHY - AR8035 */
IOMUX_PAD_CTRL(ENET_MDIO__ENET_MDIO, PAD_CTRL_ENET_MDIO),
IOMUX_PAD_CTRL(ENET_MDC__ENET_MDC, PAD_CTRL_ENET_MDC),
IOMUX_PAD_CTRL(ENET_TX_CTL__ENET_RGMII_TX_CTL, PAD_CTRL_ENET_TX),
......@@ -152,8 +150,40 @@ int dram_init(void)
}
#ifdef CONFIG_OF_BOARD_SETUP
extern struct graphic_device imx_lcdif;
int lcd_dt_simplefb_add_node(void *blob)
{
static const char compat[] = "simple-framebuffer";
static const char disabled[] = "disabled";
int off, ret;
off = fdt_add_subnode(blob, 0, "framebuffer");
if (off < 0)
return -1;
ret = fdt_setprop(blob, off, "status", disabled, sizeof(disabled));
if (ret < 0)
return -1;
ret = fdt_setprop(blob, off, "compatible", compat, sizeof(compat));
if (ret < 0)
return -1;
return fdt_setup_simplefb_node(blob, off, gd->fb_base, imx_lcdif.winSizeX,
imx_lcdif.winSizeY, imx_lcdif.winSizeX * imx_lcdif.gdfBytesPP,
"x8r8g8b8");
}
int ft_board_setup(void *blob, bd_t *bd)
{
/*
* For now, we simply always add the simplefb DT node. Later, we
* should be more intelligent, and e.g. only do this if no enabled DT
* node exists for the "real" graphics driver.
*/
lcd_dt_simplefb_add_node(blob);
return 0;
}
#endif
......@@ -232,14 +262,13 @@ int board_usb_init(int index, enum usb_init_type init)
return ret;
}
if (index == 1) {
/* Release HUB reset */
/*if (index == 1) {
#define GP_USB1_HUB_RESET IMX_GPIO_NR(1, 14)
imx_iomux_v3_setup_pad(IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 |
MUX_PAD_CTRL(WEAK_PULLUP));
MUX_PAD_CTRL(WEAK_PULLUP));
gpio_request(GP_USB1_HUB_RESET, "usb1_rst");
gpio_direction_output(GP_USB1_HUB_RESET, 1);
}
}*/
return 0;
}
......@@ -260,45 +289,15 @@ int board_usb_cleanup(int index, enum usb_init_type init)
int board_detect_hdmi(struct display_info_t const *di)
{
printf("board_detect_hdmi()");
return hdmi_hpd_status() ? 1 : 0;
}
int board_detect_gt911(struct display_info_t const *di)
{
int ret;
struct udevice *dev, *chip;
if (di->bus_gp)
gpio_direction_output(di->bus_gp, 1);
gpio_set_value(GP_GT911_RESET, 0);
mdelay(20);
gpio_direction_output(GPIRQ_GT911, di->addr_num == 0x14 ? 1 : 0);
udelay(100);
gpio_set_value(GP_GT911_RESET, 1);
mdelay(6);
gpio_set_value(GPIRQ_GT911, 0);
mdelay(50);
gpio_direction_input(GPIRQ_GT911);
ret = uclass_get_device(UCLASS_I2C, di->bus_num, &dev);
if (ret)
return 0;
ret = dm_i2c_probe(dev, di->addr_num, 0x0, &chip);
if (ret && di->bus_gp)
gpio_direction_input(di->bus_gp);
return (ret == 0);
}
// TODO: port internal MIPI DSI -> eDP display
static const struct display_info_t displays[] = {
/* hdmi */
VD_1920_1080M_60(HDMI, board_detect_hdmi, 0, 0x50),
VD_1280_720M_60(HDMI, NULL, 0, 0x50),
VD_MIPI_M101NWWB(MIPI, fbp_detect_i2c, fbp_bus_gp(0, GP_I2C1D_SN65DSI83_EN, 0, 0), 0x2c),
VD_LTK080A60A004T(MIPI, board_detect_gt911, fbp_bus_gp(0, GP_LTK08_MIPI_EN, GP_LTK08_MIPI_EN, 0), 0x5d), /* Goodix touchscreen */
VD_LCM_JM430(MIPI, fbp_detect_i2c, fbp_bus_gp(0, GP_ST1633_RESET, GP_TC358762_EN, 30), fbp_addr_gp(0x55, GP_LCM_JM430_BKL_EN, 0, 0)), /* Sitronix touch */
VD_LTK0680YTMDB(MIPI, NULL, fbp_bus_gp(0, GP_MIPI_RESET, GP_MIPI_RESET, 0), 0x0),
VD_MIPI_COM50H5N03ULC(MIPI, NULL, fbp_bus_gp(0, GP_MIPI_RESET, GP_MIPI_RESET, 0), 0x00),
VD_1920_1080M_60(HDMI, board_detect_hdmi, 0, 0x50)
};
#define display_cnt ARRAY_SIZE(displays)
#else
#define displays NULL
......@@ -307,21 +306,14 @@ static const struct display_info_t displays[] = {
int board_init(void)
{
gpio_request(GP_I2C1D_SN65DSI83_EN, "sn65dsi83_enable");
gpio_request(GP_GT911_RESET, "gt911_reset");
gpio_request(GPIRQ_GT911, "gt911_irq");
gpio_request(GP_LTK08_MIPI_EN, "lkt08_mipi_en");
gpio_direction_output(GP_GT911_RESET, 0);
#ifdef CONFIG_DM_ETH
board_eth_init(gd->bd);
#endif
#ifdef CONFIG_CMD_FBPANEL
fbp_setup_display(displays, display_cnt);
#endif
return 0;
}
// FIXME Reform: ideally we would save the env on the SD card, not the eMMC
// but setting this to 1 crashes u-boot
int board_mmc_get_env_dev(int devno)
{
return 0;
......@@ -346,17 +338,18 @@ static void addserial_env(const char* env_var)
#ifdef CONFIG_CMD_BMODE
const struct boot_mode board_boot_modes[] = {
/* 4 bit bus width */
/* 4 bit bus width */
{"emmc0", MAKE_CFGVAL(0x22, 0x20, 0x00, 0x10)},
{NULL, 0},
{NULL, 0},
};
#endif
static int fastboot_key_pressed(void)
{
gpio_request(GP_FASTBOOT_KEY, "fastboot_key");
gpio_direction_input(GP_FASTBOOT_KEY);
return !gpio_get_value(GP_FASTBOOT_KEY);
//gpio_request(GP_FASTBOOT_KEY, "fastboot_key");
//gpio_direction_input(GP_FASTBOOT_KEY);
//return !gpio_get_value(GP_FASTBOOT_KEY);
return 0;
}
void board_late_mmc_env_init(void);
......@@ -364,13 +357,28 @@ void init_usb_clk(int usbno);
static void set_env_vars(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
if (!env_get("board"))
env_set("board", "nitrogen8m_som");
env_set("board", "MNT Reform 2.0");
env_set("soc", "imx8mq");
env_set("fdtfile", "freescale/imx8mq-mnt-reform2.dtb");
env_set("imx_cpu", get_imx_type((get_cpu_rev() & 0xFF000) >> 12));
env_set("uboot_defconfig", CONFIG_DEFCONFIG);
env_set("stdin", "serial,usbkbd");
env_set("stdout", "serial,vga");
env_set("stderr", "serial,vga");
// MNT Reform 2
env_set("fdt_addr_r", "0x50000000");
env_set("ramdisk_addr_r", "0x44000000");
#ifdef MNTREFORM_BOOT_RISCOS
env_set("bootcmd", "usb start; usb reset; ext4load mmc 1 ${loadaddr} /RISCOSIMX8M; go ${loadaddr} 32");
#else
// boot normal system using distro_bootcmd
env_set("kernel_addr_r", "0x40480000");
env_set("pxefile_addr_r", "0x60000000");
env_set("scriptaddr", "0x61000000");
#endif
env_set("bootdelay", "1");
}
void board_set_default_env(void)
......@@ -382,9 +390,24 @@ void board_set_default_env(void)
board_eth_addresses();
}
static void
reset_usb_hub(void)
{
// Reform: Reset USB hub
imx_iomux_v3_setup_pad(IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(WEAK_PULLUP));
gpio_request(IMX_GPIO_NR(1, 14), "usb1_rst");
gpio_direction_output(IMX_GPIO_NR(1, 14), 1);
gpio_set_value(IMX_GPIO_NR(1, 14), 0);
mdelay(10);
gpio_set_value(IMX_GPIO_NR(1, 14), 1);
}
int board_late_init(void)
{
set_env_vars();
reset_usb_hub();
#if defined(CONFIG_USB_FUNCTION_FASTBOOT) || defined(CONFIG_CMD_DFU)
addserial_env("serial#");
if (fastboot_key_pressed()) {
......@@ -400,5 +423,28 @@ int board_late_init(void)
#endif
init_usb_clk(0);
init_usb_clk(1);
usb_init();
return 0;
}
void
board_quiesce_devices(void)
{
extern void video_hw_exit(void); /* lcdif.c */
usb_stop();
reset_usb_hub();
/*
* Linux kermel mode setting seems to fail to
* properly reset the mipi core, causing the
* screen to be shifted to the right.
*
* As a work around, we reset the lcdif and
* mipi core for it.
*/
if (images.os.os == IH_OS_LINUX)
video_hw_exit();
}
board/boundary/nitrogen8m_som/spl.c
View file @ 8e809399
......@@ -54,6 +54,8 @@ int board_mmc_getcd(struct mmc *mmc)
switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR:
return 1;
case USDHC2_BASE_ADDR:
return 1;
}
return 0;
}
......@@ -62,6 +64,10 @@ int board_mmc_getcd(struct mmc *mmc)
PAD_CTL_FSEL2)
#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
static iomux_v3_cfg_t const init_pads[] = {
#define GP_I2C1_PCA9546_RESET IMX_GPIO_NR(1, 4)
IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(0x46),
......@@ -78,16 +84,28 @@ static iomux_v3_cfg_t const init_pads[] = {
IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
#define GP_EMMC_RESET IMX_GPIO_NR(2, 10)
IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
};
static struct fsl_esdhc_cfg usdhc_cfg[] = {
{.esdhc_base = USDHC1_BASE_ADDR, .bus_width = 8,
.gp_reset = GP_EMMC_RESET},
{.esdhc_base = USDHC2_BASE_ADDR, .bus_width = 1,
.gp_reset = USDHC2_PWR_GPIO},
};
int board_mmc_init(bd_t *bis)
{
int i, ret;
/*
* According to the board_mmc_init() the following map is done:
* (U-Boot device node) (Physical Port)
......@@ -103,12 +121,20 @@ int board_mmc_init(bd_t *bis)
udelay(500);
gpio_direction_output(GP_EMMC_RESET, 1);
break;
case 1:
usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
gpio_direction_output(USDHC2_PWR_GPIO, 0);
udelay(500);
gpio_direction_output(USDHC2_PWR_GPIO, 1);
break;
default:
printf("Warning: you configured more USDHC controllers"
"(%d) than supported by the board\n", i + 1);
return -EINVAL;
}
printf("board_mmc_init: %d\n",i);
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret)
return ret;
......@@ -192,11 +218,25 @@ int board_fit_config_name_match(const char *name)
{
/* Just empty function now - can't decide what to choose */
debug("%s: %s\n", __func__, name);
return 0;
return 0;
}
#endif
static void hexdump(unsigned char *buf, int len)
{
int i;
for (i = 0; i < len; i++) {
if ((i % 16) == 0)
printf("%s%08x: ", i ? "\n" : "",
(unsigned int)&buf[i]);
printf("%02x ", buf[i]);
}
printf("\n");
}
int mx8mq_showclocks();
void board_init_f(ulong dummy)
{
int ret;
......@@ -206,6 +246,7 @@ void board_init_f(ulong dummy)
arch_cpu_init();
// without this, no uart output
board_early_init_f();
init_uart_clk(0);
timer_init();
......@@ -215,13 +256,14 @@ void board_init_f(ulong dummy)
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
ret = spl_init();
//ret = spl_init();
if (ret) {
printf("spl_init() failed: %d\n", ret);
hang();
}
enable_tzc380();
// without this, no uart output
imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
/* Adjust pmic voltage to 1.0V for 800M */
......@@ -232,5 +274,13 @@ void board_init_f(ulong dummy)
/* DDR initialization */
spl_dram_init();
mx8mq_showclocks();
// FIXME: quick DDR test
for (int i=0; i<256; i++) {
*((uint8_t*)0x42000000+i) = i;
}
hexdump(0x42000000, 512);
board_init_r(NULL, 0);
}
board/boundary/son/spl.c
View file @ 8e809399
......@@ -146,21 +146,30 @@ int power_init_boundary(void)
i2c_set_bus_num(0);
#define PF8100 0x08
#define SW1_VOLT 0x51
#define SW2_VOLT 0x59
#define SW3_CONFIG2 0x5e
#define SW3_VOLT 0x61
#define SW4_CONFIG2 0x66
#define SW4_VOLT 0x69
#define SW5_VOLT 0x71
#define SW6_VOLT 0x79
buf[0] = 0x50; /* (.90-.4)*160=.50*160=80=0x50 80/160+.4=.90 gpu/dram/arm */
buf[0] = 0x50; /* (.90-.4)*160=.50*160=80=0x50 80/160+.4=.90 */
/* dram */
ret = i2c_write(PF8100, SW2_VOLT, 1, buf, 1);
if (ret)
return ret;
/* aux_0p9 */
ret = i2c_write(PF8100, SW4_VOLT, 1, buf, 1);
if (ret)
return ret;
/* arm */
ret = i2c_write(PF8100, SW3_VOLT, 1, buf, 1);
if (ret)
return ret;
/* soc */
ret = i2c_write(PF8100, SW1_VOLT, 1, buf, 1);
if (ret)
return ret;
/*
......@@ -173,9 +182,14 @@ int power_init_boundary(void)
ret = i2c_write(PF8100, SW3_CONFIG2, 1, buf, 1);
}
buf[0] = 0x40; /* (.80-.4)*160=.40*160=64=0x40 64/160+.4=.80 vpu */
/* vpu/gpu */
buf[0] = 0x50; /* (.90-.4)*160=.50*160=80=0x50 80/160+.4=.90 */
ret = i2c_write(PF8100, SW5_VOLT, 1, buf, 1);
/* DRAM_1P1V */
buf[0] = 0x70; /* (1.10-.4)*160=.70*160=112=0x70 112/160+.4=1.10 */
ret = i2c_write(PF8100, SW6_VOLT, 1, buf, 1);
gpio_request(GP_USDHC2_VSEL, "usdhc2_vsel");
gpio_direction_output(GP_USDHC2_VSEL, 0);
return ret;
......
build.sh 0 → 100755
View file @ 8e809399
#!/bin/bash
set -exu
if [ -z ${SOURCE_DATE_EPOCH:+x} ] && git -C . rev-parse 2>/dev/null; then
export SOURCE_DATE_EPOCH=$(git log -1 --format=%ct)
fi
export CROSS_COMPILE=aarch64-linux-gnu-
export ARCH=arm
# avoid rebuilding everything every time
export KBUILD_NOCMDDEP=1
make -j$(nproc) flash.bin
cmd/boot.c
View file @ 8e809399
......@@ -31,7 +31,15 @@ static int do_go(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
addr = simple_strtoul(argv[1], NULL, 16);
printf ("## Starting application at 0x%08lX ...\n", addr);
if (argc > 2) {
printf ("## Switching to AARCH32...\n");
armv8_switch_to_el1(0, (u64)0,
(u64)0, 0,
(u64)addr,
ES_TO_AARCH32);
}
printf ("## Starting application at 0x%08lX...\n", addr);
/*
* pass address parameter as argv[0] (aka command name),
......
common/usb_kbd.c
View file @ 8e809399
......@@ -117,6 +117,8 @@ struct usb_kbd_pdata {
uint8_t old[USB_KBD_BOOT_REPORT_SIZE];
uint8_t flags;
uint8_t fakemod;
};
extern int __maybe_unused net_busy_flag;
......@@ -168,6 +170,49 @@ static int usb_kbd_translate(struct usb_kbd_pdata *data, unsigned char scancode,
{
uint8_t keycode = 0;
if(modifier == 0){
/* Emulate modifier keys for reform keyboard */
switch (scancode) {
case 0xe0:
if (pressed)
data->fakemod |= LEFT_CNTR;
else
data->fakemod &= ~LEFT_CNTR;
return 0;
case 0xe3:
if (pressed)
data->fakemod |= LEFT_GUI;
else
data->fakemod &= ~LEFT_GUI;
return 0;
case 0xe4:
if (pressed)
data->fakemod |= RIGHT_CNTR;
else
data->fakemod &= ~RIGHT_CNTR;
return 0;
case 0xe1:
if (pressed)
data->fakemod |= LEFT_SHIFT;
else
data->fakemod &= ~LEFT_SHIFT;
return 0;
case 0xe2:
if (pressed)
data->fakemod |= LEFT_ALT;
else
data->fakemod &= ~LEFT_ALT;
return 0;
case 0xe6:
if (pressed)
data->fakemod |= RIGHT_ALT;
else
data->fakemod &= ~RIGHT_ALT;
return 0;
}
modifier |= data->fakemod;
}
/* Key released */
if (pressed == 0) {
data->repeat_delay = 0;
......