When accumulated ECC is enabled, the DQ_MAP for ECC[4:7] needs to be set
to 0, i.e. 0->0, 1->1, etc., required by controller logic, even these pins
are not actually connected.

Also fix a bug when reading from DDR register to use proper accessor for
correct endianess.

Signed-off-by: York Sun <yorksun@freescale.com>

When booting with SP, RCW resides at the beginning of IFC NOR flash.

Signed-off-by: York Sun <yorksun@freescale.com>

Spin table is at the very beginning of boot code. Each core has an individual
release address within the spin table, the ft_cpu_setup fn updates the
"cpu-release-addr" property of each cpu node with the corresponding release
address.

Also fix CPU_RELEASE_ADDR to point to secondary_boot_func.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>

Secondary cores need to be released from holdoff by boot release
registers. With GPP bootrom, they can boot from main memory
directly. Individual spin table is used for each core. Spin table
and the boot page is reserved in device tree so OS won't overwrite.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>

of_bus_default_count_cells can be used to get the #address-cells
and #size-cells defined by the current node's parent node. This
is required when using of_read_number to read from FDT nodes that
can be 32 or 64 bytes depending on values defined by the parent.

Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
CC: Scott Wood <scottwood@freescale.com>

This is being done so that it can be used outside 'fdt_support.c'. Making
life more convenient when reading device node properties that can be 32
or 64 bits long.

Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>

The driver was written using old DDR3 spec which only covers low speeds.
The value would be suboptimal for higher speeds. Fix both timing according
to latest DDR3 spec, remove tCKE as an config option.

Signed-off-by: York Sun <yorksun@freescale.com>

DP-DDR is used for DPAA, separated from main memory pool for general
use. It has 32-bit bus width and use a standard DDR4 DIMM (64-bit).

Signed-off-by: York Sun <yorksun@freescale.com>

U-boot has been initializing DDR for the main memory. The presumption
is the memory stays as a big continuous block, either linear or
interleaved. This change is to support putting some DDR controllers
to separated space without counting into main memory. The standalone
memory controller could use different number of DIMM slots.

Signed-off-by: York Sun <yorksun@freescale.com>

Add support of NOR and NAND flash for simulator target.
Here
  IFC - CS0: NOR flash
  IFC - CS1: NAND flash

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

Freescale's flash control driver is using architecture specific timer API
i.e. usec2ticks

Replace usec2ticks with get_timer() (generic timer API)

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

LS2085a has 2 regions in system memory map. Region1 is default map from
where system boots. Once u-boot is moved to DDR, IFC is re-mapped to
Region2.

So, update gd->env_addr to reflect correct address.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

Since dev->req_seq value is initialized from "reg" property of fdt node,
there is posibility, that address value contained in fdt is greater than
INT_MAX, and then value in dev->req_seq is negative which led to probe()
fail.

This patch fix this problem by ensuring that req_seq is positive, unless
it's one of errno codes.

Signed-off-by: Robert Baldyga <r.baldyga@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>

Allow serial_find_console_or_panic() to work without a device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>

The sequence number support in driver model requires device tree control.
It should be skipped if CONFIG_OF_CONTROL is not defined, and should not
require functions from fdtdec.

Signed-off-by: Simon Glass <sjg@chromium.org>

The list is supposed to be terminated with a NULL name, but is not. If a
board probes a chip which does not appear in the table, U-Boot will crash
(at least on sandbox).

Signed-off-by: Simon Glass <sjg@chromium.org>

A merge error ended up repeating a similar sentence twice. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>

The get_maintainers script is a useful default, but sometimes is copies
too many people, or takes a long time to run.

Add an option to disable it and update the README.

Signed-off-by: Simon Glass <sjg@chromium.org>

This check should now be done whatever mode buildman is running in, since
we may be displaying information while building.

Signed-off-by: Simon Glass <sjg@chromium.org>

- Use _defconfig instead of _config, but still _config is working.
- Corrected README.sandbox path in ./README

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

Disable subpage write when using PMECC to prevent buggy partial page write.

This fix has been taken from linux sources (see commit
90445ff6241e2a13445310803e2efa606c61f276)

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

If the SoC has pcr, we use pcr (peripheral control register)
to enable or disable clock.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

If the SoC has pcr, we use pcr (peripheral control register)
to enable or disable clock.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

Using CPU_HAS_PCR micro to present the SoC has pcr
(peripheral control register).

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

When use pcr (peripheral control register), then we won't need
to care about the peripheral ID.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

Add NOR flash hardware init function, including SMC and PIO
configuration.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

We defined the macro pmecc_readl(b)/pmecc_writel for pmecc register access.
But in the driver we also use the readl(b)/writel.
To keep consistent, this patch make all use pmecc_readl(b)/pmecc_writel.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

This patch adds boot script support to am335x_evm

Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Tom Rini <trini@ti.com>

OMAP4: Use generic 'load' command instead of 'fatload' for 'loadbootscript' and 'loadbootenv' as already done for 'loadimage' and 'loaduimage'.

This patch uses generic 'load' command instead of 'fatload' for 'loadbootscript' and 'loadbootenv' as already done for 'loadimage' and 'loaduimage' for OMAP4 boards.

This allows to use EXT partition instead of FAT, while keeping FAT compatibility.

Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Tom Rini <trini@ti.com>

This patch implements a workaround to fix DDR3 memory issue.
The code for workaround detects PGSR0 errors and then preps for
and executes a software-controlled hard reset.In board_early_init,
where logic has been added to identify whether or not the previous
reset was a PORz. PLL initialization is skipped in the case of a
software-controlled hard reset.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Keegan Garcia <kgarcia@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>

Commit f219e013 (tools: Import Kconfiglib)
added SPDX GPL-2.0+ to this library by mistake.
It should be ISC.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Ulf Magnusson <ulfalizer@gmail.com>