options.c

	 *	- how much time you want to spend playing around
	 */
	popts->twot_en = 0;
	popts->threet_en = 0;

	/* for RDIMM and DDR4 UDIMM/discrete memory, address parity enable */
	if (popts->registered_dimm_en)
		popts->ap_en = 1; /* 0 = disable,  1 = enable */
	else
		popts->ap_en = 0; /* disabled for DDR4 UDIMM/discrete default */

	if (hwconfig_sub_f("fsl_ddr", "parity", buf)) {
		if (hwconfig_subarg_cmp_f("fsl_ddr", "parity", "on", buf)) {
			if (popts->registered_dimm_en ||
			    (CONFIG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4))
				popts->ap_en = 1;
		}
	}

	/*
	 * BSTTOPRE precharge interval
	 *
	 * Set this to 0 for global auto precharge
	 * The value of 0x100 has been used for DDR1, DDR2, DDR3.
	 * It is not wrong. Any value should be OK. The performance depends on
	 * applications. There is no one good value for all. One way to set
	 * is to use 1/4 of refint value.
	 */
	popts->bstopre = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps)
			 >> 2;

	/*
	 * Window for four activates -- tFAW
	 *
	 * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
	 * FIXME: varies depending upon number of column addresses or data
	 * FIXME: width, was considering looking at pdimm->primary_sdram_width
	 */
#if defined(CONFIG_SYS_FSL_DDR1)
	popts->tfaw_window_four_activates_ps = mclk_to_picos(ctrl_num, 1);

#elif defined(CONFIG_SYS_FSL_DDR2)
	/*
	 * x4/x8;  some datasheets have 35000
	 * x16 wide columns only?  Use 50000?
	 */
	popts->tfaw_window_four_activates_ps = 37500;

#else
	popts->tfaw_window_four_activates_ps = pdimm[0].tfaw_ps;
#endif
	popts->zq_en = 0;
	popts->wrlvl_en = 0;
#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
	/*
	 * due to ddr3 dimm is fly-by topology
	 * we suggest to enable write leveling to
	 * meet the tQDSS under different loading.
	 */
	popts->wrlvl_en = 1;
	popts->zq_en = 1;
	popts->wrlvl_override = 0;
#endif

	/*
	 * Check interleaving configuration from environment.
	 * Please refer to doc/README.fsl-ddr for the detail.
	 *
	 * If memory controller interleaving is enabled, then the data
	 * bus widths must be programmed identically for all memory controllers.
	 *
	 * Attempt to set all controllers to the same chip select
	 * interleaving mode. It will do a best effort to get the
	 * requested ranks interleaved together such that the result
	 * should be a subset of the requested configuration.
	 *
	 * if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving
	 * with 256 Byte is enabled.
	 */
#if (CONFIG_SYS_NUM_DDR_CTLRS > 1)
	if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf))
#ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
		;
#else
		goto done;
#endif
	if (pdimm[0].n_ranks == 0) {
		printf("There is no rank on CS0 for controller %d.\n", ctrl_num);
		popts->memctl_interleaving = 0;
		goto done;
	}
	popts->memctl_interleaving = 1;
#ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
	popts->memctl_interleaving_mode = FSL_DDR_256B_INTERLEAVING;
	popts->memctl_interleaving = 1;
	debug("256 Byte interleaving\n");
#else
	/*
	 * test null first. if CONFIG_HWCONFIG is not defined
	 * hwconfig_arg_cmp returns non-zero
	 */
	if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
				    "null", buf)) {
		popts->memctl_interleaving = 0;
		debug("memory controller interleaving disabled.\n");
	} else if (hwconfig_subarg_cmp_f("fsl_ddr",
					"ctlr_intlv",
					"cacheline", buf)) {
		popts->memctl_interleaving_mode =
			((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
			0 : FSL_DDR_CACHE_LINE_INTERLEAVING;
		popts->memctl_interleaving =
			((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
			0 : 1;
	} else if (hwconfig_subarg_cmp_f("fsl_ddr",
					"ctlr_intlv",
					"page", buf)) {
		popts->memctl_interleaving_mode =
			((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
			0 : FSL_DDR_PAGE_INTERLEAVING;
		popts->memctl_interleaving =
			((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
			0 : 1;
	} else if (hwconfig_subarg_cmp_f("fsl_ddr",
					"ctlr_intlv",
					"bank", buf)) {
		popts->memctl_interleaving_mode =
			((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
			0 : FSL_DDR_BANK_INTERLEAVING;
		popts->memctl_interleaving =
			((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
			0 : 1;
	} else if (hwconfig_subarg_cmp_f("fsl_ddr",
					"ctlr_intlv",
					"superbank", buf)) {
		popts->memctl_interleaving_mode =
			((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
			0 : FSL_DDR_SUPERBANK_INTERLEAVING;
		popts->memctl_interleaving =
			((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
			0 : 1;
#if (CONFIG_SYS_NUM_DDR_CTLRS == 3)
	} else if (hwconfig_subarg_cmp_f("fsl_ddr",
					"ctlr_intlv",
					"3way_1KB", buf)) {
		popts->memctl_interleaving_mode =
			FSL_DDR_3WAY_1KB_INTERLEAVING;
	} else if (hwconfig_subarg_cmp_f("fsl_ddr",
					"ctlr_intlv",
					"3way_4KB", buf)) {
		popts->memctl_interleaving_mode =
			FSL_DDR_3WAY_4KB_INTERLEAVING;
	} else if (hwconfig_subarg_cmp_f("fsl_ddr",
					"ctlr_intlv",
					"3way_8KB", buf)) {
		popts->memctl_interleaving_mode =
			FSL_DDR_3WAY_8KB_INTERLEAVING;
#elif (CONFIG_SYS_NUM_DDR_CTLRS == 4)
	} else if (hwconfig_subarg_cmp_f("fsl_ddr",
					"ctlr_intlv",
					"4way_1KB", buf)) {
		popts->memctl_interleaving_mode =
			FSL_DDR_4WAY_1KB_INTERLEAVING;
	} else if (hwconfig_subarg_cmp_f("fsl_ddr",
					"ctlr_intlv",
					"4way_4KB", buf)) {
		popts->memctl_interleaving_mode =
			FSL_DDR_4WAY_4KB_INTERLEAVING;
	} else if (hwconfig_subarg_cmp_f("fsl_ddr",
					"ctlr_intlv",
					"4way_8KB", buf)) {
		popts->memctl_interleaving_mode =
			FSL_DDR_4WAY_8KB_INTERLEAVING;
#endif
	} else {
		popts->memctl_interleaving = 0;
		printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
	}
#endif	/* CONFIG_SYS_FSL_DDR_INTLV_256B */
done:
#endif /* CONFIG_SYS_NUM_DDR_CTLRS > 1 */
	if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
		(CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
		/* test null first. if CONFIG_HWCONFIG is not defined,
		 * hwconfig_subarg_cmp_f returns non-zero */
		if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
					    "null", buf))
			debug("bank interleaving disabled.\n");
		else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
						 "cs0_cs1", buf))
			popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
		else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
						 "cs2_cs3", buf))
			popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
		else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
						 "cs0_cs1_and_cs2_cs3", buf))
			popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
		else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
						 "cs0_cs1_cs2_cs3", buf))
			popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
		else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
						"auto", buf))
			popts->ba_intlv_ctl = auto_bank_intlv(pdimm);
		else
			printf("hwconfig has unrecognized parameter for bank_intlv.\n");
		switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
		case FSL_DDR_CS0_CS1_CS2_CS3:
#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
			if (pdimm[0].n_ranks < 4) {
				popts->ba_intlv_ctl = 0;
				printf("Not enough bank(chip-select) for "
					"CS0+CS1+CS2+CS3 on controller %d, "
					"interleaving disabled!\n", ctrl_num);
			}
#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
			if (pdimm[0].n_ranks == 4)
				break;
#endif
			if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
				popts->ba_intlv_ctl = 0;
				printf("Not enough bank(chip-select) for "
					"CS0+CS1+CS2+CS3 on controller %d, "
					"interleaving disabled!\n", ctrl_num);
			}
			if (pdimm[0].capacity != pdimm[1].capacity) {
				popts->ba_intlv_ctl = 0;
				printf("Not identical DIMM size for "
					"CS0+CS1+CS2+CS3 on controller %d, "
					"interleaving disabled!\n", ctrl_num);
			}
#endif
			break;
		case FSL_DDR_CS0_CS1:
			if (pdimm[0].n_ranks < 2) {
				popts->ba_intlv_ctl = 0;
				printf("Not enough bank(chip-select) for "
					"CS0+CS1 on controller %d, "
					"interleaving disabled!\n", ctrl_num);
			}
			break;
		case FSL_DDR_CS2_CS3:
#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
			if (pdimm[0].n_ranks < 4) {
				popts->ba_intlv_ctl = 0;
				printf("Not enough bank(chip-select) for CS2+CS3 "
					"on controller %d, interleaving disabled!\n", ctrl_num);
			}
#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
			if (pdimm[1].n_ranks < 2) {
				popts->ba_intlv_ctl = 0;
				printf("Not enough bank(chip-select) for CS2+CS3 "
					"on controller %d, interleaving disabled!\n", ctrl_num);
			}
#endif
			break;
		case FSL_DDR_CS0_CS1_AND_CS2_CS3:
#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
			if (pdimm[0].n_ranks < 4) {
				popts->ba_intlv_ctl = 0;
				printf("Not enough bank(CS) for CS0+CS1 and "
					"CS2+CS3 on controller %d, "
					"interleaving disabled!\n", ctrl_num);
			}
#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
			if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) {
				popts->ba_intlv_ctl = 0;
				printf("Not enough bank(CS) for CS0+CS1 and "
					"CS2+CS3 on controller %d, "
					"interleaving disabled!\n", ctrl_num);
			}
#endif
			break;
		default:
			popts->ba_intlv_ctl = 0;
			break;
		}
	}

	if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) {
		if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf))
			popts->addr_hash = 0;
		else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
					       "true", buf))
			popts->addr_hash = 1;
	}

	if (pdimm[0].n_ranks == 4)
		popts->quad_rank_present = 1;

	ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
	if (popts->registered_dimm_en) {
		popts->rcw_override = 1;
		popts->rcw_1 = 0x000a5a00;
		if (ddr_freq <= 800)
			popts->rcw_2 = 0x00000000;
		else if (ddr_freq <= 1066)
			popts->rcw_2 = 0x00100000;
		else if (ddr_freq <= 1333)
			popts->rcw_2 = 0x00200000;
		else
			popts->rcw_2 = 0x00300000;
	}

	fsl_ddr_board_options(popts, pdimm, ctrl_num);

	return 0;
}

void check_interleaving_options(fsl_ddr_info_t *pinfo)
{
	int i, j, k, check_n_ranks, intlv_invalid = 0;
	unsigned int check_intlv, check_n_row_addr, check_n_col_addr;
	unsigned long long check_rank_density;
	struct dimm_params_s *dimm;
	int first_ctrl = pinfo->first_ctrl;
	int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;

	/*
	 * Check if all controllers are configured for memory
	 * controller interleaving. Identical dimms are recommended. At least
	 * the size, row and col address should be checked.
	 */
	j = 0;
	check_n_ranks = pinfo->dimm_params[first_ctrl][0].n_ranks;
	check_rank_density = pinfo->dimm_params[first_ctrl][0].rank_density;
	check_n_row_addr =  pinfo->dimm_params[first_ctrl][0].n_row_addr;
	check_n_col_addr = pinfo->dimm_params[first_ctrl][0].n_col_addr;
	check_intlv = pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode;
	for (i = first_ctrl; i <= last_ctrl; i++) {
		dimm = &pinfo->dimm_params[i][0];
		if (!pinfo->memctl_opts[i].memctl_interleaving) {
			continue;
		} else if (((check_rank_density != dimm->rank_density) ||
		     (check_n_ranks != dimm->n_ranks) ||
		     (check_n_row_addr != dimm->n_row_addr) ||
		     (check_n_col_addr != dimm->n_col_addr) ||
		     (check_intlv !=
			pinfo->memctl_opts[i].memctl_interleaving_mode))){
			intlv_invalid = 1;
			break;
		} else {
			j++;
		}

	}
	if (intlv_invalid) {
		for (i = first_ctrl; i <= last_ctrl; i++)
			pinfo->memctl_opts[i].memctl_interleaving = 0;
		printf("Not all DIMMs are identical. "
			"Memory controller interleaving disabled.\n");
	} else {
		switch (check_intlv) {
		case FSL_DDR_256B_INTERLEAVING:
		case FSL_DDR_CACHE_LINE_INTERLEAVING:
		case FSL_DDR_PAGE_INTERLEAVING:
		case FSL_DDR_BANK_INTERLEAVING:
		case FSL_DDR_SUPERBANK_INTERLEAVING:
#if (3 == CONFIG_SYS_NUM_DDR_CTLRS)
				k = 2;
#else
				k = CONFIG_SYS_NUM_DDR_CTLRS;
#endif
			break;
		case FSL_DDR_3WAY_1KB_INTERLEAVING:
		case FSL_DDR_3WAY_4KB_INTERLEAVING:
		case FSL_DDR_3WAY_8KB_INTERLEAVING:
		case FSL_DDR_4WAY_1KB_INTERLEAVING:
		case FSL_DDR_4WAY_4KB_INTERLEAVING:
		case FSL_DDR_4WAY_8KB_INTERLEAVING:
		default:
			k = CONFIG_SYS_NUM_DDR_CTLRS;
			break;
		}
		debug("%d of %d controllers are interleaving.\n", j, k);
		if (j && (j != k)) {
			for (i = first_ctrl; i <= last_ctrl; i++)
				pinfo->memctl_opts[i].memctl_interleaving = 0;
			if ((last_ctrl - first_ctrl) > 1)
				puts("Not all controllers have compatible interleaving mode. All disabled.\n");
		}
	}
	debug("Checking interleaving options completed\n");
}

int fsl_use_spd(void)
{
	int use_spd = 0;

#ifdef CONFIG_DDR_SPD
	char buffer[HWCONFIG_BUFFER_SIZE];
	char *buf = NULL;

	/*
	 * Extract hwconfig from environment since we have not properly setup
	 * the environment but need it for ddr config params
	 */
	if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
		buf = buffer;

	/* if hwconfig is not enabled, or "sdram" is not defined, use spd */
	if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) {
		if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf))
			use_spd = 1;
		else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",
					       "fixed", buf))
			use_spd = 0;
		else
			use_spd = 1;
	} else
		use_spd = 1;
#endif

	return use_spd;
}