define there own I/O functions.
          (Needed for the pcs440ep board).
        - The default I/O Functions are again 8 Bit accesses.
        - Added CONFIG_CMD_IDE for the pcs440ep Board.

Signed-off-by: Heiko Schocher <hs@denx.de>

Signed-off-by: Wolfgang Denk <wd@denx.de>

platforms wishing to display RAM diagnostics in addition to size,
can do so, on one line, in their own board_add_ram_info()
implementation.

this consequently eliminates CONFIG_ADD_RAM_INFO.

Thanks to Stefan for the hint.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

This patch has been sent on:
- 6 Jun 2007

Many users of PCI config read routines tend to ignore the function
ret value, and are only concerned about the contents of *val. Based
on this, pci_hose_read_config_{byte,word}_via_dword should initialize
the *val on dword read error.

Without this fix, for example, we'll go on scanning bus with vendor or
header_type uninitialized. This brings many unnecessary config trials.

Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>

Signed-off-by: Stefan Roese <sr@denx.de>

Signed-off-by: Stefan Roese <sr@denx.de>

Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>

introduced in the implement board_add_ram_info patch as I was cleaning out the
magic numbers.  sorry.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

includes build fixes.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

add board_add_ram_info, to make memory diagnostic output more
consistent. u-boot banner output now looks like:

DRAM:  256 MB (DDR1, 64-bit, ECC on)

and for boards with SDRAM on the local bus, a line such as this is
added:

SDRAM: 64 MB (local bus)

also replaced some magic numbers with their equivalent define names.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

The patch split the PIB init code from pci.c to a single file board/freescale/common/pq-mds-pib.c
And add Qoc3 ATM card support for MPC8360EMDS and MPC832XEMDS board.

Signed-off-by Tony Li <tony.li@freescale.com>

Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>

The 85xx code now relies on CONFIG_HAS_ETH0 to determine whether
to update TSEC1's device-tree node, so we need to add it
to all the boards with TSECs.  Do this for 83xx and 86xx, too,
since they will eventually do something similar.

Signed-off-by: Andy Fleming <afleming@freescale.com>

The PCIe bus that the ULI M1575 is connected to has no possible way of
needing more than the fixed amount of IO & Memory space needed by the ULI.

So make it use far less IO & memory space and have it use the shared LAW.  This
free's up a LAW for PCIe1 IO space.  Also reduce the amount of IO space needed
by each bus.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

It looks like we had a merge issue that duplicated a bit of code
in ft_board_setup.  Also, we need to set CONFIG_HAS_ETH0 to get
the MAC address properly set in the device tree on boot for TSEC1

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Minor cleanups to confirm to the u-boot coding style.
Some german expressions -> english.
HCU5 enforces a unique IP adress for a given slot in the rack.

Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>

Make ecc initialisation robust, as DDR2-ECC errors may be generated
while zeroing the RAM.

Return 16 bytes (a cacheline) less than the available memory, as the
board and/or PPC440EPx might have problems accessing the last bytes.

Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

Forgot to cast of_flat_tree to ulong.

Signed-off-by: Andy Fleming <afleming@freescale.com>