PPC4xx:HCU4/5 cleanup ecc/sdram init

Make ecc initialisation robust, as DDR2-ECC errors may be generated
while zeroing the RAM.

Return 16 bytes (a cacheline) less than the available memory, as the
board and/or PPC440EPx might have problems accessing the last bytes.

Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>

board/netstal/hcu5/sdram.c

@@ -36,7 +36,7 @@
 #include <asm/mmu.h>
 #include <ppc440.h>
 
-void sysLedSet(u32 value);
+void hcu_led_set(u32 value);
 void dcbz_area(u32 start_address, u32 num_bytes);
 void dflush(void);
 
@@ -138,7 +138,7 @@ static int wait_for_dlllock(void)
 void sdram_panic(const char *reason)
 {
 	printf("\n%s: reason %s",  __FUNCTION__,  reason);
-	sysLedSet(0xff);
+	hcu_led_set(0xff);
 	while (1) {
 	}
 	/* Never return */
@@ -197,6 +197,13 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes,
 	mfsdram(DDR0_00, val);
 	mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
 
+	/*
+	 * Clear possible errors
+	 * If not done, then we could get an interrupt later on when
+	 * exceptions are enabled.
+	 */
+	mtspr(mcsr, mfspr(mcsr));
+
 	/* Set 'int_mask' parameter to functionnal value */
 	mfsdram(DDR0_01, val);
 	mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) |
@@ -244,7 +251,6 @@ long int initdram (int board_type)
 		sdram_panic(INVALID_HW_CONFIG);
 		break;
 	}
-	dram_size -= 16 * 1024 * 1024;
 	mtsdram(DDR0_07, 0x00090100);
 	/*
 	 * TCPD=200 cycles of clock input is required to lock the DLL.
@@ -283,6 +289,7 @@ long int initdram (int board_type)
 	/*
 	 * Program tlb entries for this size (dynamic)
 	 */
+	remove_tlb(CFG_SDRAM_BASE, 256 << 20);
 	program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
 
 	/*
@@ -291,6 +298,8 @@ long int initdram (int board_type)
 	 */
 	program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0);
 
+	/* Diminish RAM to initialize */
+	dram_size = dram_size - 32 ;
 #ifdef CONFIG_DDR_ECC
 	/*
 	 * If ECC is enabled, initialize the parity bits.