Skip to content
Snippets Groups Projects
Select Git revision
  • master default protected
  • early-display
  • variant-emmc-nvme-boot
  • 2023-01-25
  • v3
  • variant-emmc-nvme-boot
  • 2020-06-01
7 results
Search by author
  • Any Author
  • Jack Humbert Jack Humbert jackhumbert
1 author
  1. Feb 24, 2014
    • Ying Zhang's avatar
      SPL: powerpc: expand SPL's length to 128K · ee4d6511
      Ying Zhang authored 
      
1. The SPL's length of SDCARD boot has not enough,expand the SPL's
length to 128K.
2. deleted unused symbol: CONFIG_SYS_RUN_INDDR

Signed-off-by: default avatarYing Zhang <b40530@freescale.com>
Reviewed-by: default avatarYork Sun <yorksun@freescale.com>
      ee4d6511
    • Shengzhou Liu's avatar
      powerpc/t2081qds: Add T2081 QDS board support · 254887a5
      Shengzhou Liu authored 
      
T2081 QDS is a high-performance computing evaluation, development and
test platform supporting the T2081 QorIQ Power Architecture processor.

T2081QDS board Overview
-----------------------
- T2081 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
- 2MB shared L2 and 512KB L3 CoreNet platform cache (CPC)
- CoreNet fabric supporting coherent and noncoherent transactions with
  prioritization and bandwidth allocation
- 32-/64-bit DDR3/DDR3LP SDRAM memory controller with ECC and interleaving
- Ethernet interfaces:
  - Two on-board 10M/100M/1G bps RGMII ports
  - Two 10Gbps XFI with on-board SFP+ cage
  - 1Gbps/2.5Gbps SGMII Riser card
  - 10Gbps XAUI Riser card
- Accelerator:
  - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
- SerDes:
  - 8 lanes up to 10.3125GHz
  - Supports SGMII, HiGig, XFI, XAUI and Aurora debug,
- IFC:
  - 512MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA
- eSPI:
  - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
- USB:
  - Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB)
- PCIe:
  - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
- eSDHC:
  - Supports various SD/SDHC/SDXC/eMMC devices with adapter cards and
    voltage translators
- I2C:
  - Four I2C controllers.
- UART:
  - Dual 4-pins UART serial ports

Signed-off-by: default avatarShengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: default avatarYork Sun <yorksun@freescale.com>
      254887a5
  3. Feb 07, 2014
    • Tom Rini's avatar
      x600: Switch to CONFIG_PHYLIB · 1a78d28d
      Tom Rini authored 
      
Now that the designware ethernet driver uses phylib we need to turn it
on here.

Acked-by: default avatarStefan Roese <sr@denx.de>
Signed-off-by: default avatarTom Rini <trini@ti.com>
      1a78d28d
    • Alexey Brodkin's avatar
      net/designware - switch driver to phylib usage · 92a190aa
      Alexey Brodkin authored 
      
With this change driver will benefit from existing phylib and thus
custom phy functionality implemented in the driver will go away:
 * Instantiation of the driver is now much shorter - 2 parameters
instead of 4.
 * Simplified phy management/functoinality in driver is replaced with
rich functionality of phylib.
 * Support of custom phy initialization is now done with existing
"board_phy_config".

Note that after this change some previously used config options
(driver-specific PHY configuration) will be obsolete and they are simply
substituted with similar options of phylib.

For example:
 * CONFIG_DW_AUTONEG - no need in this one. Autonegotiation is enabled
by default.
 * CONFIG_DW_SEARCH_PHY - if one wants to specify attached phy
explicitly CONFIG_PHY_ADDR board config option has to be used, otherwise
automatically the first discovered on MDIO bus phy will be used

I believe there's no need now in "doc/README.designware_eth" because
user only needs to instantiate the driver with "designware_initialize"
whose prototype exists in "include/netdev.h".

Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Mischa Jonker <mjonker@synopsys.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Amit Virdi <amit.virdi@st.com>
Cc: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: default avatarAlexey Brodkin <abrodkin@synopsys.com>
      92a190aa
    • Alexey Brodkin's avatar
      arc: add AXS101 board support · a7069ddf
      Alexey Brodkin authored 
      
AXS101 is a new generation of devlopment boards from Synopsys that houses
ASIC with ARC700 and lots of DesignWare peripherals:

 * DW APB UART
 * DW Mobile Storage (MMC/SD)
 * DW I2C
 * DW GMAC

Signed-off-by: default avatarAlexey Brodkin <abrodkin@synopsys.com>

Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Francois Bedard <fbedard@synopsys.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
      a7069ddf
    • Alexey Brodkin's avatar
      arc: add Arcangel4 board support · 66712b8b
      Alexey Brodkin authored 
      
Arcangel4 is a FPGA-based development board that is used for prototyping and
verificationof of both ARC hardware (CPUs) and software running upon CPU.

This board avaialble in 2 flavours:
 * Little-endian (arcangel4)
 * Big-endian (arcangel4-be)

Signed-off-by: default avatarAlexey Brodkin <abrodkin@synopsys.com>

Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Francois Bedard <fbedard@synopsys.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
      66712b8b
    • Alexey Brodkin's avatar
      arc: bdinfo, image and arc-specific init functions declarations support · bc5d5428
      Alexey Brodkin authored 
      
Signed-off-by: default avatarAlexey Brodkin <abrodkin@synopsys.com>

Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Francois Bedard <fbedard@synopsys.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
      bc5d5428
  5. Feb 06, 2014
    • Tom Rini's avatar
      include/usb/s3c_udc.h: Add <asm/sizes.h> · dbf3de2d
      Tom Rini authored 
      
With e0059eae switching to using SZ_1K, we need to #include <asm/sizes.h>
here for everyone to build still.

Signed-off-by: default avatarTom Rini <trini@ti.com>
      dbf3de2d
    • Michal Simek's avatar
      fpga: zynqpl: Add support for zc7015 device · 31993d6a
      Michal Simek authored 
      
Just extend tables with this new device.

Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
      31993d6a
    • Marek Vasut's avatar
      usb: mv_udc: Rename to ci_udc · f016f8ca
      Marek Vasut authored 
      
The mv_udc is not marvell-specific anymore. The mv_udc is used to drive
generic ChipIdea CI13xxx series OTG cores, so rename the driver to ci_udc
instead.

Signed-off-by: default avatarMarek Vasut <marex@denx.de>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Stefano Babic <sbabic@denx.de>
      f016f8ca
    • Łukasz Majewski's avatar
      usb:udc:samsung: Zero copy approach for data passed to Samsung's UDC driver · e0059eae
      Łukasz Majewski authored 
      
The Samsung's UDC driver is not anymore copying data from USB requests to
aligned internal buffers. Now it works directly in data allocated in the
upper layers like UMS, DFU, THOR.

This change is possible since those gadgets now must take care to allocate
buffers aligned to cache line (CONFIG_SYS_CACHELINE_SIZE).

This can be achieved by using DEFINE_CACHE_ALIGN_BUFFER() or
ALLOC_CACHE_ALIGN_BUFFER() macros. Those take care to allocate buffer
aligned to cache line in both starting address and its size.
Sometimes it is enough to just use memalign() with size being a
multiplication of cache line size.

Test condition
- test HW + measurement: Trats - Exynos4210 rev.1
- test HW Trats2 - Exynos4412 rev.1
400 MiB compressed rootfs image download with `thor 0 mmc 0`

Measurement:
Transmission speed: 27.04 MiB/s

Signed-off-by: default avatarLukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>
      e0059eae
  7. Feb 05, 2014
  9. Feb 04, 2014
  11. Feb 03, 2014
  13. Jan 24, 2014