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  • Jack Humbert Jack Humbert jackhumbert
1 author
  1. Mar 04, 2014
  3. Feb 26, 2014
  5. Feb 25, 2014
    • Masahiro Yamada's avatar
      kbuild: Move linker sciript check to prepare1 · 4a377552
      Masahiro Yamada authored 
      
Same as the previous commit.
Move sanity check to prepare1 target to avoid nasty troubles.

Before this commit, LDSCRIPT existence was not checked
when it was specified by CONFIG_SYS_LDSCRIPT.
Now LDSCRIPT existence is checked for all boards.

$(wildcard $(LDSCRIPT)) must point to the linker scripts
with absolute path.
Otherwise, make will terminate with a false error
on out-of-tree build.

Signed-off-by: default avatarMasahiro Yamada <yamada.m@jp.panasonic.com>
      4a377552
  7. Feb 24, 2014
    • Haijun.Zhang's avatar
      powerpc/mpc8536DS:Increase binary size for mpc8536DS board · c6e8f49a
      Haijun.Zhang authored 
      
u-boot binary size for Freescale mpc8536DS platforms is 512KB.
This has been reached to upper limit of the platforms and causig
linker error. So increase the u-boot binary size to 768KB.

Signed-off-by: default avatarHaijun Zhang <Haijun.Zhang@freescale.com>
Reviewed-by: default avatarYork Sun <yorksun@freescale.com>
      c6e8f49a
    • Ying Zhang's avatar
      powerpc: p1010rdb: Enable p1010rdb to start from NAND/SD/SPI flash with SPL · c9e1f588
      Ying Zhang authored 
      
In the previous patches, we introduced the SPL/TPL fraamework.
For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The
SPL was loaded by the code from the internal on-chip ROM. The SPL initializes
the DDR according to the SPD and loads the final uboot image into DDR, then
jump to the DDR to begin execution.

For NAND booting way, the nand SPL has size limitation on some board(e.g.
P1010RDB), it can not be more than 8KB, we can call it "minimal SPL", So the
dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is
loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD
and loads the final uboot image into DDR,then jump to the DDR to begin execution.

This patch enabled SPL/TPL for P1010RDB to support starting from NAND/SD/SPI
flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL.
Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to
execute, so the section .resetvec is no longer needed.

Signed-off-by: default avatarYing Zhang <b40530@freescale.com>
Reviewed-by: default avatarYork Sun <yorksun@freescale.com>
      c9e1f588
    • Ying Zhang's avatar
      SPL: P1022DS: fix the problem booting from spi flash · 27585bd3
      Ying Zhang authored 
      
There was no enough memory for malloc in SPL booting from spi flash, so
relayout the memory in SPL: reduce the memory for global data from 16K
Bytes to 4K Bytes, save the space for malloc.

Signed-off-by: default avatarYing Zhang <b40530@freescale.com>
Reviewed-by: default avatarYork Sun <yorksun@freescale.com>
      27585bd3
    • Ying Zhang's avatar
      SPL: P2020RDB: fix the problem booting from spi flash · 5a89fa92
      Ying Zhang authored 
      
There was no enough stack in SPL, so the buffer needed in SPL is to malloc
from memory pool and to repalce the temporary variable.

Signed-off-by: default avatarYing Zhang <b40530@freescale.com>
Reviewed-by: default avatarYork Sun <yorksun@freescale.com>
      5a89fa92
    • Ying Zhang's avatar
      SPL: powerpc: expand SPL's length to 128K · ee4d6511
      Ying Zhang authored 
      
1. The SPL's length of SDCARD boot has not enough,expand the SPL's
length to 128K.
2. deleted unused symbol: CONFIG_SYS_RUN_INDDR

Signed-off-by: default avatarYing Zhang <b40530@freescale.com>
Reviewed-by: default avatarYork Sun <yorksun@freescale.com>
      ee4d6511
    • Shengzhou Liu's avatar
      powerpc/t2081qds: Add T2081 QDS board support · 254887a5
      Shengzhou Liu authored 
      
T2081 QDS is a high-performance computing evaluation, development and
test platform supporting the T2081 QorIQ Power Architecture processor.

T2081QDS board Overview
-----------------------
- T2081 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
- 2MB shared L2 and 512KB L3 CoreNet platform cache (CPC)
- CoreNet fabric supporting coherent and noncoherent transactions with
  prioritization and bandwidth allocation
- 32-/64-bit DDR3/DDR3LP SDRAM memory controller with ECC and interleaving
- Ethernet interfaces:
  - Two on-board 10M/100M/1G bps RGMII ports
  - Two 10Gbps XFI with on-board SFP+ cage
  - 1Gbps/2.5Gbps SGMII Riser card
  - 10Gbps XAUI Riser card
- Accelerator:
  - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
- SerDes:
  - 8 lanes up to 10.3125GHz
  - Supports SGMII, HiGig, XFI, XAUI and Aurora debug,
- IFC:
  - 512MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA
- eSPI:
  - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
- USB:
  - Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB)
- PCIe:
  - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
- eSDHC:
  - Supports various SD/SDHC/SDXC/eMMC devices with adapter cards and
    voltage translators
- I2C:
  - Four I2C controllers.
- UART:
  - Dual 4-pins UART serial ports

Signed-off-by: default avatarShengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: default avatarYork Sun <yorksun@freescale.com>
      254887a5
    • Masahiro Yamada's avatar
      arm: delete unused macro CONFIG_ARCH_DEVICE_TREE · f55e911f
      Masahiro Yamada authored 
      
Signed-off-by: default avatarMasahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Rajeshwari Birje <rajeshwari.s@samsung.com>
Cc: Inderpal Singh <inderpal.singh@linaro.org>
      f55e911f
  9. Feb 22, 2014
  11. Feb 21, 2014