The current code use all the voltage range support by the host
controller to do the validation.  This will cause problem when
the host supports Low Voltage Range.  Change the validation
voltage to be based on board setup.

Signed-off-by: Li Yang <leoli@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

The max clock of MMC is 52MHz

Signed-off-by: Jerry Huang <Changm-Ming.Huang@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

After booting the u-boot, and first using some SD card (such as Sandisk 2G SD
card), because the field 'clock' of struct mmc is zero, this will cause
the read transfer is always active and SDHC DATA line is always active,
therefore, driver can't handle the next command.

Therefore, we use mmc_set_clock to setup both the data structure and HW
to the initial clock speed of 400000Hz.

Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Fix clock divider for COM57H5M10XRC display.
The previous setting caused flicker.

Tested on Qong (EVBLite with COM57H5M10XRC).

Signed-off-by: Stefano Babic <sbabic@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>

Signed-off-by: Wolfgang Denk <wd@denx.de>

Signed-off-by: Wolfgang Denk <wd@denx.de>

Add ARM Relocation Support

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Add ARM Relocation Support

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Add ARM Relocation Support

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Add ARM Relocation Support

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Some DaVinci boards are using flags that are no longer valid
So remove them.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Signed-off-by: Guido Classen <clagix@gmail.com>
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>

Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>

Signed-off-by: Asen Dimov <dimov@ronetix.at>

Signed-off-by: Asen Dimov <dimov@ronetix.at>

Signed-off-by: Asen Dimov <dimov@ronetix.at>

Signed-off-by: Asen Dimov <dimov@ronetix.at>

Signed-off-by: Asen Dimov <dimov@ronetix.at>

Signed-off-by: Asen Dimov <dimov@ronetix.at>

Recent GCC (4.4+) performs out-of-line epilogues in some cases, when
optimizing for size.  It causes a link error for _restgpr_30_x (and similar)
if libgcc is not linked.

It actually increases size with very small binaries, due to the fixed size
of the out-of-line code, and not having any functions that actually need to
restore more than 2 or 3 registers.  But I don't see a way to turn it off,
other than asking GCC to optimize for speed -- which may also increase
size for some boards.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Acked-by: Wolfgang Denk <wd@denx.de>

This patch fixes the acadia_nand and kilauea_nand linker scripts
which have been missing in commit ee8028b7 [ppc4xx: Cleanup for
partial linking and --gc-sections]

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bernhard Weirich <Bernhard.Weirich@riedel.net>

Make code build with older tool chains.

Signed-off-by: Wolfgang Denk <wd@denx.de>

This patch fix a problem for the pcie enumeration for mpc83xx cpus.  Without
this we will not  get correct value in hose->regions[...].

The pointer *reg in function mpc83xx_pcie_init_bus() shall not be changed.
Because we will use this pointer as a parameter to call function
mpc83xx_pcie_register_hose().

Signed-off-by: Baidu Boy <liucai.lfn@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

On the P1022, the pins which drive the video display (DIU) are muxed with the
local bus controller (LBC), so if the DIU is active, the pins need to be
temporarily muxed to LBC whenever accessing NOR flash.

The code which handled this transition is checking and changing the wrong
bits in PMUXCR.

Also add a follow-up read after a write to NOR flash if we're going to
mux back to DIU after the write, as described in the P1022 RM.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

eSDHC host controller reset results in clearing of snoop bit also.
This patch sets the SNOOP bit after the completion of host controller reset.
Without this patch mmc reads are not consistent.

Signed-off-by: P.V.Suresh <pala@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

According to Freescale reference manuals (eg section "13.4.4.2
Programming the UPMs" of the P4080 Reference Manual):

"Since the result of any update to the MxMR/MDR register must be in
effect before the dummy read or write to the UPM region, a write to
MxMR/MDR should be followed immediately by a read of MxMR/MDR."

The UPM on a custom P4080-based board did not work without performing
a read of MxMR/MDR after a write.

Signed-off-by: John Schmoller <jschmoller@xes-inc.com>
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

The following commit:

commit 46e91674
Author: Peter Tyser <ptyser@xes-inc.com>
Date:   Tue Nov 3 17:52:07 2009 -0600

    tsec: Force TBI PHY to 1000Mbps full duplex in SGMII mode

Removed setting Auto-Neg by default, however this is believed to be
proper default configuration for initialization of the TBI interface.

Instead we explicitly set CONFIG_TSEC_TBICR_SETTINGS for the
XPedite5370 & XPedite5500 boards that use a Broadcomm PHY which require
Auto-Neg to be disabled to function properly.

This addresses a breakage on the P2020 DS & MPC8572 DS boards when used
with an SGMII riser card.  We also remove setting
CONFIG_TSEC_TBICR_SETTINGS on the P1_P2_RDB family of boards as now the
default setting is sufficient for them.

Additionally, we clean up the code a bit to remove an unnecessary second
define.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Peter Tyser <ptyser@xes-inc.com>
Tested-by: Peter Tyser <ptyser@xes-inc.com>

DECLARE_GLOBAL_DATA_PTR declarations in functions are inherently
troublesome with various compilers (e.g. gcc 4.5)

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Reuse the gd->tbl value for timestamp and add gd->lastinc for lastinc bss
values in the OMAP timer driver.

The usage of bss values in drivers before initialisation of bss is forbidden.
In that special case some data in .rel.dyn gets corrupted.

Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
Tested-by: Steve Sakoman <steve.sakoman@linaro.org>
Tested-by: John Rigby <john.rigby@linaro.org>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Tested-by: Heiko Schocher <hs@denx.de>
Tested-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

The DM6446 does not build due to the ARM
relocation patch.

Also the board does not build in the NOR
mode. Changed default to NAND to ensure
no build failure.
While at it removed CONFIG_CMD_KGDB

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

This change allows the davinci timer functions to be used before
relocation since it avoids using static variables prior to BSS being
made available.

The code is based on that used in the at91 timers, modified to use
a davinci specific hardware timer. It also maintains reset_timer()
to allow deprecated timer usage to continue to work (for example,
in nand_base.c)

Signed-off-by: Nick Thompson <nick.thompson@ge.com>
Tested-by: Ben Gardiner <bengardiner@nanometrics.ca>
Tested-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Tested-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

This file has been synced (copy) from Linux source code.
This commit was based on kernel 2.6.32.
It updates gigabit related phy registers and basic definitions.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>