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Commit 2c1764ef authored by P.V.Suresh's avatar P.V.Suresh Committed by Kumar Gala
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fsl_esdhc: Set the eSHDC DMACTL[SNOOP] bit after resetting the controller


eSDHC host controller reset results in clearing of snoop bit also.
This patch sets the SNOOP bit after the completion of host controller reset.
Without this patch mmc reads are not consistent.

Signed-off-by: default avatarP.V.Suresh <pala@freescale.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 9fd84915
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...@@ -384,10 +384,6 @@ static int esdhc_init(struct mmc *mmc) ...@@ -384,10 +384,6 @@ static int esdhc_init(struct mmc *mmc)
int ret = 0; int ret = 0;
u8 card_absent; u8 card_absent;
/* Enable cache snooping */
if (cfg && !cfg->no_snoop)
esdhc_write32(&regs->scr, 0x00000040);
/* Reset the entire host controller */ /* Reset the entire host controller */
esdhc_write32(&regs->sysctl, SYSCTL_RSTA); esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
...@@ -395,6 +391,10 @@ static int esdhc_init(struct mmc *mmc) ...@@ -395,6 +391,10 @@ static int esdhc_init(struct mmc *mmc)
while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout) while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
udelay(1000); udelay(1000);
/* Enable cache snooping */
if (cfg && !cfg->no_snoop)
esdhc_write32(&regs->scr, 0x00000040);
esdhc_write32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); esdhc_write32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
/* Set the initial clock speed */ /* Set the initial clock speed */
......
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