In the previous patches, we introduced the SPL/TPL fraamework.
For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The
SPL was loaded by the code from the internal on-chip ROM. The SPL initializes
the DDR according to the SPD and loads the final uboot image into DDR, then
jump to the DDR to begin execution.

For NAND booting way, the nand SPL has size limitation on some board(e.g.
P1010RDB), it can not be more than 8KB, we can call it "minimal SPL", So the
dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is
loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD
and loads the final uboot image into DDR,then jump to the DDR to begin execution.

This patch enabled SPL/TPL for P1010RDB to support starting from NAND/SD/SPI
flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL.
Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to
execute, so the section .resetvec is no longer needed.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

There was no enough memory for malloc in SPL booting from spi flash, so
relayout the memory in SPL: reduce the memory for global data from 16K
Bytes to 4K Bytes, save the space for malloc.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

There was no enough stack in SPL, so the buffer needed in SPL is to malloc
from memory pool and to repalce the temporary variable.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

1. The SPL's length of SDCARD boot has not enough,expand the SPL's
length to 128K.
2. deleted unused symbol: CONFIG_SYS_RUN_INDDR

Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

T2081 QDS is a high-performance computing evaluation, development and
test platform supporting the T2081 QorIQ Power Architecture processor.

T2081QDS board Overview
-----------------------
- T2081 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
- 2MB shared L2 and 512KB L3 CoreNet platform cache (CPC)
- CoreNet fabric supporting coherent and noncoherent transactions with
  prioritization and bandwidth allocation
- 32-/64-bit DDR3/DDR3LP SDRAM memory controller with ECC and interleaving
- Ethernet interfaces:
  - Two on-board 10M/100M/1G bps RGMII ports
  - Two 10Gbps XFI with on-board SFP+ cage
  - 1Gbps/2.5Gbps SGMII Riser card
  - 10Gbps XAUI Riser card
- Accelerator:
  - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
- SerDes:
  - 8 lanes up to 10.3125GHz
  - Supports SGMII, HiGig, XFI, XAUI and Aurora debug,
- IFC:
  - 512MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA
- eSPI:
  - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
- USB:
  - Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB)
- PCIe:
  - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
- eSDHC:
  - Supports various SD/SDHC/SDXC/eMMC devices with adapter cards and
    voltage translators
- I2C:
  - Four I2C controllers.
- UART:
  - Dual 4-pins UART serial ports

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

Now that the designware ethernet driver uses phylib we need to turn it
on here.

Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>

With this change driver will benefit from existing phylib and thus
custom phy functionality implemented in the driver will go away:
 * Instantiation of the driver is now much shorter - 2 parameters
instead of 4.
 * Simplified phy management/functoinality in driver is replaced with
rich functionality of phylib.
 * Support of custom phy initialization is now done with existing
"board_phy_config".

Note that after this change some previously used config options
(driver-specific PHY configuration) will be obsolete and they are simply
substituted with similar options of phylib.

For example:
 * CONFIG_DW_AUTONEG - no need in this one. Autonegotiation is enabled
by default.
 * CONFIG_DW_SEARCH_PHY - if one wants to specify attached phy
explicitly CONFIG_PHY_ADDR board config option has to be used, otherwise
automatically the first discovered on MDIO bus phy will be used

I believe there's no need now in "doc/README.designware_eth" because
user only needs to instantiate the driver with "designware_initialize"
whose prototype exists in "include/netdev.h".

Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Mischa Jonker <mjonker@synopsys.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Amit Virdi <amit.virdi@st.com>
Cc: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

AXS101 is a new generation of devlopment boards from Synopsys that houses
ASIC with ARC700 and lots of DesignWare peripherals:

 * DW APB UART
 * DW Mobile Storage (MMC/SD)
 * DW I2C
 * DW GMAC

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Francois Bedard <fbedard@synopsys.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>

Arcangel4 is a FPGA-based development board that is used for prototyping and
verificationof of both ARC hardware (CPUs) and software running upon CPU.

This board avaialble in 2 flavours:
 * Little-endian (arcangel4)
 * Big-endian (arcangel4-be)

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Francois Bedard <fbedard@synopsys.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Francois Bedard <fbedard@synopsys.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>

With e0059eae switching to using SZ_1K, we need to #include <asm/sizes.h>
here for everyone to build still.

Signed-off-by: Tom Rini <trini@ti.com>

Just extend tables with this new device.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

The mv_udc is not marvell-specific anymore. The mv_udc is used to drive
generic ChipIdea CI13xxx series OTG cores, so rename the driver to ci_udc
instead.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Stefano Babic <sbabic@denx.de>

The Samsung's UDC driver is not anymore copying data from USB requests to
aligned internal buffers. Now it works directly in data allocated in the
upper layers like UMS, DFU, THOR.

This change is possible since those gadgets now must take care to allocate
buffers aligned to cache line (CONFIG_SYS_CACHELINE_SIZE).

This can be achieved by using DEFINE_CACHE_ALIGN_BUFFER() or
ALLOC_CACHE_ALIGN_BUFFER() macros. Those take care to allocate buffer
aligned to cache line in both starting address and its size.
Sometimes it is enough to just use memalign() with size being a
multiplication of cache line size.

Test condition
- test HW + measurement: Trats - Exynos4210 rev.1
- test HW Trats2 - Exynos4412 rev.1
400 MiB compressed rootfs image download with `thor 0 mmc 0`

Measurement:
Transmission speed: 27.04 MiB/s

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>

Signed-off-by: Tom Rini <trini@ti.com>

describe a set of default features that distros can rely on being available.
having this common definition means that distros can easily support systems
implementing them.

Signed-off-by: Dennis Gilmore <dennis@ausil.us>

Add support for U-BOOT SPL. NOR and RAM mode are supported.
There are 3 images in NOR flash. u-boot.img, dtb and kernel.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

It speeds up writing a lot.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Command provides just dump subcommand for showing clock
frequencies in a soc.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Stefano Babic <sbabic@denx.de>

IFC registers can be of type Little Endian or big Endian depending upon
Freescale SoC. Here SoC defines the register type of IFC IP.

So update acessor functions with common IFC acessor functions to take care
both type of endianness.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>

The new prototype and the final series was moved from Micron to Spansion
to have a better reset sequence that is easier to support.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: York Sun <yorksun@freescale.com>

This define can be used if the ubi boot partition (defined for all
Keymile boards with KM_UBI_PARTITION_NAME_BOOT #define to ubi0) needs
some additionnal boot options.

This is the case for the kmp204x boards since u-boot does not support
NAND Flash subpage accesses on this platform, an additionnal argument
that defines the VID offstet must be given to the kernel.

The UBI cmd line option now looks like this "ubi.mtd=ubi0,2048" on this
platform.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: York Sun <yorksun@freescale.com>

The kmcoge4 board is the product board derived from the kmlion1
prototype. The main difference between the 2 boards is that the kmcoge4
does not configure the Local Bus controller for LCS2.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
[York Sun: Minor change to boards.cfg to keep targets in order]
Signed-off-by: York Sun <yorksun@freescale.com>

This patch adds support for using some GPIOs that are connected to the
I2C bus to force the bus lines state and perform some bus deblocking
sequences.

The KM common deblocking algorithm from board/keymile/common/common.c is
used. The GPIO lines used for deblocking the I2C bus are some external
GPIOs provided by the QRIO CPLD:
  - SCL = GPIOA_20
  - SDA = GPIOA_21

The QRIO GPIOs act in an open-drain-like manner, for 0 the line is
driven low and for 1 the GPIO is set as input and the line gets
pulled-up.

Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: York Sun <yorksun@freescale.com>

Make use of the QRIO1 32bit register at 0x20 as bootcounter register
Check for BOOTCOUNT_MAGIC pattern when before bootcounter value is read

Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
[York Sun: Minor change to commit message]
Signed-off-by: York Sun <yorksun@freescale.com>

This covers only non-L2 switch ethernet interfaces i.e.
RGMII and SGMII interface for both T1040RDB and T1042RDB_PI

T1040RDB is configured as serdes protocol 0x66 which can
support following interfaces
    2 RGMIIS on DTSEC4, DTSEC5
    1 SGMII on DTSEC3

T1042RDB_PI is configured as serdes protocol 0x06 which can
support following interfaces
    2 RGMIIS on DTSEC4, DTSEC5

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
[York Sun: Minor change in commit message]
Signed-off-by: York Sun <yorksun@freescale.com>

Add usb2 node entry to hwconfig default

Remove DDR controller interleaving from hwconfig

Move SPI related macros out of "#ifdef CONFIG_SPIFLASH"

Add CONFIG_SYS_CSPR2_EXT to make CPLD accessible in u-boot

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Fix commit message]
Signed-off-by: York Sun <yorksun@freescale.com>

Add usb2 node entry in "hwconfig string"

Remove controller interleaving from hwconfig string as T1040
has only one DDR conroller

SPI related macros which were earlier under #ifdef CONFIG_SPIFLASH
are move outside so that they are defined for all cases as these
macros are also used by other u-boot code

Add CONFIG_SYS_CSPR2_EXT to make CPLD accessible

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
[York Sun: Minor change to commit message]
Signed-off-by: York Sun <yorksun@freescale.com>

Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5
    Define MDIO related configs
    Added eth.c file
    Update t1040.c to support RGMII and SGMII
    Update t1040qds.c to support ethernet
    Define the PHY address

Signed-off-by: Arpit Goel <B44344@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: remove dash from commit message]
Signed-off-by: York Sun <yorksun@freescale.com>

Add the USB host boot support for the am43xx evm
Add the macros to boot from a usb drive in uBoot

Signed-off-by: Dan Murphy <dmurphy@ti.com>

Add SPL support to be able to detect a USB Mass Storage device
connected to a USB host.  Once a USB Mass storage device is detected
the SPL will load the u-boot.img from a FAT partition to target address.

Signed-off-by: Dan Murphy <dmurphy@ti.com>

Move the FAT functions to a common location for reuse.

Signed-off-by: Dan Murphy <dmurphy@ti.com>

We do not have to define CONFIG_MPC5xxx in board config headers
(and start.S) because it is defined in arch/powerpc/cpu/mpc5xxx/config.mk.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

The function os_free() returns nothing.
Its return type should be "void" rather than "void *".

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Define CONFIG_MPC86xx in arch/powerpc/cpu/mpc86xx/config.mk
because all target boards with mpc86xx cpu define it.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Define CONFIG_MPC85xx in arch/powerpc/cpu/mpc85xx/config.mk
because all target boards with mpc85xx cpu define it.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

We do not have to define CONFIG_MPC824X in board config headers
because it is defined in arch/powerpc/cpu/mpc824x/config.mk.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

We do not have to define CONFIG_MPC512X in board config headers
because it is defined in arch/powerpc/cpu/mpc512x/config.mk.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

We do not have to define CONFIG_MPC83xx in board config headers
because it is defined in arch/powerpc/cpu/mpc83xx/config.mk.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

We do not have to define CONFIG_4xx in board config headers
because it is defined in arch/powerpc/cpu/ppc4xx/config.mk.

include/configs/JSE.h defines "CONFIG_4x", not "CONFIG_4xx".
I believe it is a typo because "CONFIG_4x" is not used at all
in other files.
So, I also deleted "CONFIG_4x" in include/configs/JSE.h.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>