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  1. May 24, 2016
  2. May 23, 2016
  3. May 17, 2016
    • Simon Glass's avatar
      dm: scsi: Rename CONFIG_CMD_SCSI to CONFIG_SCSI · c649e3c9
      Simon Glass authored
      
      This option currently enables both the command and the SCSI functionality.
      Rename the existing option to CONFIG_SCSI since most of the code relates
      to the feature.
      
      Signed-off-by: default avatarSimon Glass <sjg@chromium.org>
      c649e3c9
    • Peng Fan's avatar
      dm: spi: soft_spi: switch to use linux compatible string · 102412c4
      Peng Fan authored
      
      1. Support compatible string "spi-gpio" which is used by Linux
         Linux use different bindings, so use UBOOT_COMPAT and
         LINUX_COMPAT to differentiate them.
      2. Introduce SPI_MASTER_NO_RX and SPI_MASTER_NO_TX to handle
         no rx or no tx case.
      3. Tested on i.MX6 UltraLite board with 74LV595 spi-gpio chip.
      
      Signed-off-by: default avatarPeng Fan <van.freenix@gmail.com>
      Cc: Simon Glass <sjg@chromium.org>
      Cc: Przemyslaw Marczak <p.marczak@samsung.com>
      Reviewed-by: default avatarSimon Glass <sjg@chromium.org>
      102412c4
    • Stephen Warren's avatar
      video: tegra: refuse to bind to disabled dcs · 54693cbd
      Stephen Warren authored
      
      This prevents the following boot-time message on any board where only the
      first DC is in use, yet the DC's DT node is enabled:
      
      stdio_add_devices: Video device failed (ret=-22)
      
      (This happens on at least Harmony, Ventana, and likely any other Tegra20
      board with display enabled other than Seaboard).
      
      The Tegra DC's DT node represents a display controller. It may itself
      drive an integrated RGB display output, or be used by some other display
      controller such as HDMI. For this reason the DC node itself is not
      enabled/disabled in DT; the DC itself is considered a shared resource, not
      the final (board-specific) display output. The node should instantiate a
      display output driver only if the rgb subnode is enabled. Other output
      drivers are free to use the DC if they are enabled and their DT node
      references the DC's DT node. Adapt the Tegra display drivers' bind()
      routine to only bind to the DC's DT node if the RGB subnode is enabled.
      
      Now that the display driver does the right thing, remove the workaround
      for this issue from Seaboard's DT file.
      
      Cc: Thierry Reding <treding@nvidia.com>
      Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
      Acked-by: default avatarThierry Reding <treding@nvidia.com>
      Reviewed-by: default avatarSimon Glass <sjg@chromium.org>
      54693cbd
    • Stefan Agner's avatar
      imx: imx-common: print i.MX 7 SoC names consistently · 249092fa
      Stefan Agner authored
      
      According to the product website, the full names are i.MX 7Solo
      and i.MX 7Dual, whereas the short form is i.MX7S and i.MX7D. Be
      consistent and print the short form for both supported i.MX 7 SoCs.
      
      Signed-off-by: default avatarStefan Agner <stefan@agner.ch>
      Reviewed-by: default avatarFabio Estevam <fabio.estevam@nxp.com>
      249092fa
    • Stefan Agner's avatar
      imx: imx7d: fix ahb clock mux 1 · f716bf11
      Stefan Agner authored
      
      The clock parent of the AHB root clock when using mux option 1
      is the SYS PLL 270MHz clock. This is specified in  Table 5-11
      Clock Root Table of the i.MX 7Dual Applications Processor
      Reference Manual.
      
      While it could be a documentation error, the 270MHz parent is
      also mentioned in the boot ROM configuration in Table 6-28: The
      clock is by default at 135MHz due to a POST_PODF value of 1
      (=> divider of 2).
      
      Signed-off-by: default avatarStefan Agner <stefan@agner.ch>
      f716bf11
    • Stefan Agner's avatar
      imx: iomux-v3: fix UART input selects · 1fb51333
      Stefan Agner authored
      Several UART input selects are missing. The fourth input select
      for UART2_TX_DATA_ALT0 is actually also missing in the documentation.
      (at least in Rev. B of the i.MX 7Dual Reference Manual). However,
      when looking at the tables of other input selects, it is very natural
      that there must be an input select for the UART2_TX_DATA_ALT0 pad.
      The Colibri iMX7 also uses that pad for UART2 RX (in DTE mode), and
      it was required to set that particular input select register to get a
      working UART2.
      1fb51333
    • Eric Nelson's avatar
      imx: mx6: mx6sl_pins: add GPIO variant for SD1_DAT5 · 9f623326
      Eric Nelson authored
      
      This patch adds the IOMUX setting for using SD1_DAT5 as GPIO5:9.
      
      Signed-off-by: default avatarEric Nelson <eric@nelint.com>
      Reviewed-by: default avatarPeng Fan <van.freenix@gmail.com>
      9f623326
  4. May 12, 2016
  5. May 06, 2016
    • Anatolij Gustschin's avatar
      socfpga: fix broken build if CONFIG_ETH_DESIGNWARE disabled · 5289c5fa
      Anatolij Gustschin authored
      
      Building without ethernet driver doesn't work. Fix it.
      
      Signed-off-by: default avatarAnatolij Gustschin <agust@denx.de>
      Cc: Marek Vasut <marex@denx.de>
      5289c5fa
    • Marek Vasut's avatar
      ARM: socfpga: Disable USB OC protection on SoCrates · 268da813
      Marek Vasut authored
      
      This is mandatory, otherwise the USB does not work.
      
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Stefan Roese <sr@denx.de>
      Cc: Dinh Nguyen <dinguyen@kernel.org>
      268da813
    • Peng Fan's avatar
      imx6: cache: disable L2 before touching Auxiliary Control Register · ad7af5d7
      Peng Fan authored
      
      According PL310 TRM, Auxiliary Control Register
      "
      The register must be written to using a secure access, and it can be
      read using either a secure or a NS access. If you write to this register
      with a NS access, it results in a write response with a DECERR response,
      and the register is not updated. Writing to this register with the L2
      cache enabled, that is, bit[0] of L2 Control Register set to 1,
      results in a SLVERR.
      "
      
      So If L2 cache is already enabled by ROM, chaning value of ACR
      will cause SLVERR and uboot hang.
      
      Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
      Cc: Stefano Babic <sbabic@denx.de>
      Cc: Fabio Estevam <fabio.estevam@nxp.com>
      ad7af5d7
    • Russ Dill's avatar
      ARM: am33xx: Fix DDR initialization delays · b67d6b00
      Russ Dill authored
      
      The current delays in the DDR initialization routines for am33xx
      architectures are sometimes not running long enough leading to DDR
      init errors. On am437x, this shows up as an L3 NOC error after the
      kernel boots. This is due to the timer not being initialized
      properly, but instead still containing the timer init values from
      the boot ROM which cause timers to expire in 1/4th the time
      required.
      
      timer_init is typically not called until board_init_r, however on
      am33xx/am43xx udelay is required in sdram_init which is called
      from board_init_f, so a call to timer_init is required earlier.
      
      Note that this issue introduced in v2015.01 by:
      
      b352dde1 "am33xx: Drop timer_init call from s_init".
      
      Although this could instead fixed by reverting said commit, it
      would cause timer_init to be called twice in both SPL and non-SPL
      cases. This gives a little more fine grained control and also
      matches what is being done on omap-command and fsl-layerscape.
      
      Signed-off-by: default avatarRuss Dill <russ.dill@ti.com>
      b67d6b00
    • Stephen Warren's avatar
      ARM: fix ifdefs in ARMv8 lowlevel_init() · 11661193
      Stephen Warren authored
      
      Commit 724219a6 "ARM: always perform per-CPU GIC init" removed some
      ifdefs to unify the MULTIENTRY-vs-non-MULTIENTRY paths. However, the
      wrong endif was removed. This patch adds back that missing endif, and
      adds a new ifdef to match the endif the now-correctly-terminated block
      used to match against. Use "git show -U25 724219a6" to see enough
      context to make the original issue clear.
      
      In practical terms, this makes no difference to runtime behaviour. The
      code that was incorrectly compiled into the binary when ifndef MULTIENTRY
      is a no-op for other cases, since branch_if_master evaluates to a hard-
      coded jump. The only issues were:
      
      - A few extra instructions were added to the binary.
      - The comment on the endif at the very end of the function, indicating
      which ifdef it matched, were wrong.
      
      An alternative might be to simply fix the comment on that trailing ifdef,
      but that only addresses the second point above, not the first.
      
      Fixes: 724219a6 ("ARM: always perform per-CPU GIC init")
      Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
      Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
      Reviewed-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      11661193
    • Robert P. J. Day's avatar
      Fix various typos, scattered over the code. · 1cc0a9f4
      Robert P. J. Day authored
      Spelling corrections for (among other things):
      
      * environment
      * override
      * variable
      * ftd (should be "fdt", for flattened device tree)
      * embedded
      * FTDI
      * emulation
      * controller
      1cc0a9f4
  6. May 04, 2016
    • Stephen Warren's avatar
      ARM: tegra: enable GPU node by compatible value · d9b6f58e
      Stephen Warren authored
      
      In current Linux kernel Tegra DT files, 64-bit addresses are represented
      in unit addresses as a pair of comma-separated 32-bit values. Apparently
      this is no longer the correct representation for simple busses, and the
      unit address should be represented as a single 64-bit value. If this is
      changed in the DTs, arm/arm/mach-tegra/board2.c:ft_system_setup() will no
      longer be able to find and enable the GPU node, since it looks up the node
      by name.
      
      Fix that function to enable nodes based on their compatible value rather
      than their node name. This will work no matter what the node name is, i.e
      for DTs both before and after any rename operation.
      
      Cc: Thierry Reding <treding@nvidia.com>
      Cc: Alexandre Courbot <acourbot@nvidia.com>
      Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
      Signed-off-by: default avatarTom Warren <twarren@nvidia.com>
      d9b6f58e
  7. May 02, 2016
  8. Apr 30, 2016
  9. Apr 27, 2016
    • Hans de Goede's avatar
      sunxi: mctl_mem_matches: Add missing memory barrier · bfb33f0b
      Hans de Goede authored
      
      We are running with the caches disabled when mctl_mem_matches gets called,
      but the cpu's write buffer is still there and can still get in the way,
      add a memory barrier to fix this.
      
      This avoids mctl_mem_matches always returning false in some cases, which
      was resulting in:
      
      U-Boot SPL 2015.07 (Apr 14 2016 - 18:47:26)
      DRAM: 1024 MiB
      
      U-Boot 2015.07 (Apr 14 2016 - 18:47:26 +0200) Allwinner Technology
      
      CPU:   Allwinner A23 (SUN8I)
      DRAM:  512 MiB
      
      Where 512 MiB is the right amount, but the DRAM controller would be
      initialized for 1024 MiB.
      
      Signed-off-by: default avatarHans de Goede <hdegoede@redhat.com>
      Acked-by: default avatarIan Campbell <ijc@hellion.org.uk>
      bfb33f0b
  10. Apr 25, 2016
  11. Apr 24, 2016
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