- May 03, 2008
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Wolfgang Denk authored
Some config.mk files reference $(CC) to test for specific tool chain features, so make sure $(CC) gets set before including any such config files. This patch replaces commit b7166e05 ("ColdFire: Get information from the correct GCC"). Signed-off-by:
Wolfgang Denk <wd@denx.de>
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Jean-Christophe PLAGNIOL-VILLARD authored
start.S:183:1: warning: "ICMR" redefined In file included from start.S:33: include/asm/arch/pxa-regs.h:935:1: warning: this is the location of the previous definition start.S:187:1: warning: "RCSR" redefined ... Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Jean-Christophe PLAGNIOL-VILLARD authored
Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by:
Wolfgang Denk <wd@denx.de>
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Kumar Gala authored
Make the flags use -Os like all other boards Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Stefan Roese authored
This patch fixes a problem with the month being read and written incorrectly (offset by one). This only gets visible by also using the Linux driver (rtc-m41t80). Tested on AMCC Canyonlands. Signed-off-by:
Stefan Roese <sr@denx.de>
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- May 01, 2008
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Wolfgang Denk authored
Onenand needs a version of memcpy() which performs 16 bit accesses only; make sure the name does not conflict with the standard function. Signed-off-by:
Wolfgang Denk <wd@denx.de>
- Apr 30, 2008
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Jean-Christophe PLAGNIOL-VILLARD authored
Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Timur Tabi authored
Some 86xx chips use CCB as the base clock for the I2C, and others used CCB/2. There is no pattern that can be used to determine which chips use which frequency, so the only way to determine is to look up the actual SOC designation and use the right value for that SOC. Signed-off-by:
Timur Tabi <timur@freescale.com>
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TsiChung Liew authored
The ethernet hang is caused by receiving buffer in DRAM is not yet ready due to access cycles require longer time in DRAM. Relocate DMA buffer descriptors from DRAM to internal SRAM. Signed-off-by:
TsiChung Liew <Tsi-Chung.Liew@freescale.com>
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TsiChung Liew authored
Signed-off-by:
Luigi Comio Mantellini <luigi.mantellini@idf-hit.com> Signed-off-by:
TsiChung Liew <Tsi-Chung.Liew@freescale.com>
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TsiChung Liew authored
Signed-off-by:
Kurt Mahan <kmahan@freescale.com> Signed-off-by:
TsiChung Liew <Tsi-Chung.Liew@freescale.com>
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Dirk Behme authored
Fix warnings nv_nand.c: In function 'saveenv': env_nand.c:200: warning: passing argument 3 of 'nand_write' from incompatible pointer type env_nand.c: In function 'env_relocate_spec': env_nand.c:275: warning: passing argument 3 of 'nand_read' from incompatible pointer type if compiled for davinci_schmoogie_config. Signed-off-by:
Dirk Behme <dirk.behme@gmail.com> Ack by: Sergey Kubushyn <ksi@koi8.net>
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Anatolij Gustschin authored
MPC8610HPCD board adds -O2 gcc option to PLATFORM_CPPFLAGS causing overriding default -Os option. New gcc (ver. 4.2.2) produces warnings while compiling net/net.c file with -O2 option. The patch is an attempt to fix this. Signed-off-by:
Anatolij Gustschin <agust@denx.de>
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Sascha Laue authored
Signed-off-by:
Sascha Laue <sascha.laue@liebherr.com> Signed-off-by:
Wolfgang Denk <wd@denx.de>
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Sascha Laue authored
Signed-off-by:
Sascha Laue <sascha.laue@liebherr.com>
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Wolfgang Denk authored
Signed-off-by:
Wolfgang Denk <wd@denx.de>
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Wolfgang Denk authored
This problem shows up with parallel builds only; it results in somewhat cryptic error messages like $ JOBS=-j6 MAKEALL netstar Configuring for netstar board... arm-linux-ld: cannot find -lgeneric make[1]: *** [eeprom.srec] Error 1 A few boards (like netstar and voiceblue) need some libraries for building; however, the board Makefile does not contain any such dependencies which may cause problems with parallel builds. Adding such dependencies is difficult as we would also have to provide build rules, which already exist in the respective library Makefiles. To solve this, we make sure that all libraries get built before the board code. Signed-off-by:
Wolfgang Denk <wd@denx.de>
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Stefan Roese authored
This patch changes the Canyonlands/Glacier fixed DDR2 controller setup used for NAND booting to match the values needed for the new 512MB DIMM modules shipped with the productions boards: Crucial: CT6464AC667.8FB Signed-off-by:
Stefan Roese <sr@denx.de>
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Stefan Roese authored
This patch fixes a problem with DIMMs that have 8 banks. Now the MCIF0_MBxCF register will be setup correctly for this setup too. This was noticed with the 512MB DIMM on Canyonlands/Glacier. Signed-off-by:
Stefan Roese <sr@denx.de>
- Apr 29, 2008
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Wolfgang Denk authored
Signed-off-by:
Wolfgang Denk <wd@denx.de>
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Wolfgang Denk authored
Signed-off-by:
Wolfgang Denk <wd@denx.de>
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Wolfgang Denk authored
Signed-off-by:
Wolfgang Denk <wd@denx.de>
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Wolfgang Denk authored
Signed-off-by:
Wolfgang Denk <wd@denx.de>
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Kumar Gala authored
Newer gcc's might be configured to enable autovectorization by default. If we happen to build with one of those compilers we will get SPE instructions in random code. -mno-spe disables the compiler for automatically generating SPE instructions without our knowledge. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
All the 85xx and 86xx UM describe the register as timing_cfg_3 not as ext_refrec. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
Rename init_addr and init_ext_addr to match the docs between 85xx and 86xx. Both now use 'init_addr' and 'init_ext_addr'. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
* adjust __spin_table alignment to match ePAPR v0.94 spec * loop over all cpus when determing who is up. This fixes an issue if the "boot cpu" isn't core0. The "boot cpu" will already be in the cpu_up_mask so there is no harm * Added some protection in the code to ensure proper behavior. These changes are explicitly needed but don't hurt: - Added eieio to ensure the "hot word" of the table is written after all other table updates have occurred. - Added isync to ensure we don't prefetch loading of table entries until we a released These issues we raised by Dave Liu. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Yuri Tikhonov authored
LWMON5 DSPIC POST uses the watch-dog scratch register. So, make the CFG_DSPIC_TEST_ADDR definition more readable. Signed-off-by:
Yuri Tikhonov <yur@emcraft.com>
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Stefan Roese authored
Signed-off-by:
Stefan Roese <sr@denx.de>
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Yuri Tikhonov authored
Some boards (e.g. lwmon5) need rather a frequent watch-dog kicking. Since the time it takes for the flush_cache() function to complete its job depends on the size of data being flushed, one may encounter watch-dog resets on such boards when, for example, download big files over ethernet. Signed-off-by:
Yuri Tikhonov <yur@emcraft.com>
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Stefan Roese authored
Signed-off-by:
Stefan Roese <sr@denx.de>
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