- May 25, 2016
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Andre Przywara authored
The originally committed .dts files for the Pine64 were from an early proof-of-concept version and should have never been committed upstream. Replace them with much more mature versions, which also use a different naming scheme. Please note that at this point there is at least one binding which has not been agreed upon, so this is subject to change. Signed-off-by:
Andre Przywara <andre.przywara@arm.com> Acked-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
Hans de Goede <hdegoede@redhat.com>
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Bernhard Nortmann authored
This addresses a cosmetic issue when booting a sunxi device over USB (FEL mode), where the SPL currently would just print "Trying to boot from ". The patch fixes that to properly read "Trying to boot from FEL". Signed-off-by:
Bernhard Nortmann <bernhard.nortmann@web.de> Reviewed-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
Hans de Goede <hdegoede@redhat.com>
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Siarhei Siamashka authored
The current SPL header, created by the 'mksunxiboot' tool, has size 32 bytes. But the code in the boot ROM stores the information about the boot media at the offset 0x28 before passing control to the SPL. For example, when booting from the SD card, the magic number written by the boot ROM is 0. And when booting from the SPI flash, the magic number is 3. NAND and eMMC probably have their own special magic numbers too. Currently the corrupted byte is a part of one of the instructions in the reset vectors table: b reset ldr pc, _undefined_instruction ldr pc, _software_interrupt <- Corruption happens here ldr pc, _prefetch_abort ldr pc, _data_abort ldr pc, _not_used ldr pc, _irq ldr pc, _fiq In practice this does not cause any visible problems, but it's still better to fix it. As a bonus, the reported boot media type can be later used in the 'spl_boot_device' function, but this is out of the scope of this patch. Signed-off-by:
Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
Hans de Goede <hdegoede@redhat.com>
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Chen-Yu Tsai authored
The A80 uses the AXP809 as its primary PMIC. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Reviewed-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
Hans de Goede <hdegoede@redhat.com>
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- May 24, 2016
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Mugunthan V N authored
Fix typo error for cpsw device name with proper device address Signed-off-by:
Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by:
Tom Rini <trini@konsulko.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
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Mugunthan V N authored
Add syscon node to cpsw device node to read mac address from efuse. Signed-off-by:
Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by:
Tom Rini <trini@konsulko.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
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Mugunthan V N authored
Add syscon node to cpsw device node to read mac address from efuse. Signed-off-by:
Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by:
Tom Rini <trini@konsulko.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
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Mugunthan V N authored
Add platforms specific phy mode configuration bits to be used to configure phy mode in control module. Signed-off-by:
Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by:
Tom Rini <trini@konsulko.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
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Michal Simek authored
Extending Kconfig for adding new platform is a lot of work for nothing. Setting SYS_CONFIG_NAME directly in Kconfig and remove all dependencies on TARGET_ZYNQ_* options including SPL. As a side-effect it also remove custom init folder for ps7_init_gpl.* files. Folder is chosen based on device-tree file. Signed-off-by:
Michal Simek <michal.simek@xilinx.com>
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Michal Simek authored
Support RAM and MMC boot mode in SPL also with SPL_FIT images. In MMC boot mode two boot options are available: 1) Boot flow with ATF(EL3) and full U-Boot(EL2): aarch64-linux-gnu-objcopy -O binary bl31.elf bl31.bin mkimage -A arm64 -O linux -T kernel -C none -a 0xfffe5000 -e 0xfffe5000 -d bl31.bin atf.ub cp spl/boot.bin <sdcard fat partition> cp atf.ub <sdcard fat partition> cp u-boot.bin <sdcard fat partition> 2) Boot flow with full U-Boot(EL3): cp spl/boot.bin <sdcard> cp u-boot*.img <sdcard> 3) emmc boot mode dd if=/dev/zero of=sd.img bs=1024 count=1024 parted sd.img mktable msdos parted sd.img mkpart p fat32 0% 100% kpartx -a sd.img mkfs.vfat /dev/mapper/loop0p1 mount /dev/mapper/loop0p1 /mnt/ cp spl/boot.bin /mnt cp u-boot.img /mnt cp u-boot.bin /mnt cp atf.ub /mnt umount /dev/mapper/loop0p1 kpartx -d sd.img cp sd.img /tftpboot/ and program it via u-boot tftpb 10000 sd.img mmcinfo mmc write 10000 0 $filesize mmc rescan mmc part ls mmc 0 psu_init() function contains low level SoC setup generated for every HW design by Xilinx design tools. xil_io.h is only supporting file to fix all dependencies from tools. The same solution was used on Xilinx Zynq. The patch also change CONFIG_SYS_INIT_SP_ADDR to the end of OCM which stays at the same location all the time. Bootrom expects starting address to be at 0xfffc0000 that's why this address is SPL_TEXT_BASE. Signed-off-by:
Michal Simek <michal.simek@xilinx.com>
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Michal Simek authored
Add missing u-boot,dm-pre-reloc to get IPs initialized. Signed-off-by:
Michal Simek <michal.simek@xilinx.com>
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Alexander Graf authored
The GIC ranges in the zynqmp device tree are only 4kb aligned. Since commit 12e14066f we automatically deal with aliases GIC regions though, so we can map them transparently into guests even on 64kb page size systems. This patch makes use of that features and sets GICC and GICV to 64kb aligned and sized regions. Signed-off-by:
Alexander Graf <agraf@suse.de> Signed-off-by:
Michal Simek <michal.simek@xilinx.com>
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Michal Simek authored
If ps7_post_config() is defined call it. It is enabling for example level shifters for PL bitstreams. Signed-off-by:
Michal Simek <michal.simek@xilinx.com>
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Michal Simek authored
Enable minimal function to be able to compile SPL_LOAD_FIT. Signed-off-by:
Michal Simek <michal.simek@xilinx.com>
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Masahiro Yamada authored
Commit 9f56917a ("dm: core: make simple-bus compatible to simple-mfd") made possible to import the following commit: Linux commit: bc5ba9b98435bf76d92e0954da1784695aa449f1 The SLCR (System-Level Control Registers) block is an MFD (Multi Function Device) rather than a bus. "simple-mfd" seems a more suitable compatible string than "simple-bus". Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
Michal Simek <michal.simek@xilinx.com>
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Marek Vasut authored
Implement support for saving ARM register R4 early during boot using save_boot_params . Implement support for decoding the stored register R4 value in spl_boot_device() to obtain boot device from which the SoC booted. This way, the SPL will always load U-Boot from the same device from which the SPL itself booted instead of using hard-coded boot device. This functionality is useful for example when booting sama5d2-xplained from SD card, where by default the SPL would try loading the U-Boot from eMMC and fail. This is because eMMC is on SDHCI0 (BOOT_DEVICE_MMC1), while SD slot is on SDHCI1 (BOOT_DEVICE_MMC2) and the SPL was hard-wired to always boot from BOOT_DEVICE_MMC1. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by:
Andreas Bießmann <andreas@biessmann.org>
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Wenyou Yang authored
Add the UPLL clock and master clock as a clock source for getting the generated clock frequency to complete its clock sources support. Signed-off-by:
Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by:
Andreas Bießmann <andreas@biessmann.org>
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Wenyou Yang authored
Before enabling a generated clock whose source is from the UPLL clock, check and enable the UPLL clock. Signed-off-by:
Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by:
Andreas Bießmann <andreas@biessmann.org>
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Wenyou Yang authored
The board supports following features: - Boot media support: NAND Flash/SPI Flash - Support ethernet - Support USB mass storage Signed-off-by:
Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by:
Andreas Bießmann <andreas@biessmann.org>
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Wenyou Yang authored
They will be used on SAMA5D2 PTC board. Signed-off-by:
Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by:
Andreas Bießmann <andreas@biessmann.org>
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- May 23, 2016
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Masahiro Yamada authored
Commit 11661193 ("ARM: fix ifdefs in ARMv8 lowlevel_init()") accidentally inverted the logic of CONFIG_ARMV8_MULTIENTRY. Fixes: 11661193 ("ARM: fix ifdefs in ARMv8 lowlevel_init()") Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by:
Stephen Warren <swarren@nvidia.com>
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- May 18, 2016
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Shengzhou Liu authored
During DDR-2133 operation, the transmit data eye margins determined during the memory controller initialization may be sub-optimal, set DEBUG_29[12] and DEBUG_29[13:16] = 4'b0100 before MEM_EN is set. Signed-off-by:
Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Alex Porosanu authored
Some SOCs, specifically the ones in the C29x familiy can have multiple security engines. This patch adds a system configuration define which indicates the maximum number of SEC engines that can be found on a SoC. Signed-off-by:
Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Alex Porosanu authored
Freescale PPC SoCs do not hard-code security engine's Job Ring 0 address, rather a define is used. This patch adds the same functionality to the ARM based SoCs (i.e. LS1/LS2 and i.MX parts) Signed-off-by:
Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Qianyu Gong authored
MMCSD_MODE_FAT has been renamed to MMCSD_MODE_FS by commit 205b4f33. Signed-off-by:
Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Qianyu Gong authored
MMCSD_MODE_FAT has be renmaed to MMCSD_MODE_FS by commit 205b4f33. Signed-off-by:
Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Qianyu Gong authored
init_early_memctl_regs() is also be called in board_early_init_f(). So remove the duplicated call in spl code. Signed-off-by:
Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Alison Wang authored
As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b06, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by:
Alison Wang <alison.wang@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Yuan Yao authored
The address value and size value set for QSPI dts node "reg" property have type of u64 on arm64. Signed-off-by:
Yuan Yao <yao.yuan@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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- May 17, 2016
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Alex Porosanu authored
For Qoriq PPC&ARM v7 platforms, the crypto node is being fixup'ed in order to update the SEC internal version (aka SEC ERA). This patch adds the same functionality to the ARMv8 SoCs. Signed-off-by:
Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Shengzhou Liu authored
The initial training for the DDRC may provide results that are not optimized. The workaround provides better read timing margins. Signed-off-by:
Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Shengzhou Liu authored
Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by:
Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Simon Glass authored
This option currently enables both the command and the SCSI functionality. Rename the existing option to CONFIG_SCSI since most of the code relates to the feature. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Peng Fan authored
1. Support compatible string "spi-gpio" which is used by Linux Linux use different bindings, so use UBOOT_COMPAT and LINUX_COMPAT to differentiate them. 2. Introduce SPI_MASTER_NO_RX and SPI_MASTER_NO_TX to handle no rx or no tx case. 3. Tested on i.MX6 UltraLite board with 74LV595 spi-gpio chip. Signed-off-by:
Peng Fan <van.freenix@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Reviewed-by:
Simon Glass <sjg@chromium.org>
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Stephen Warren authored
This prevents the following boot-time message on any board where only the first DC is in use, yet the DC's DT node is enabled: stdio_add_devices: Video device failed (ret=-22) (This happens on at least Harmony, Ventana, and likely any other Tegra20 board with display enabled other than Seaboard). The Tegra DC's DT node represents a display controller. It may itself drive an integrated RGB display output, or be used by some other display controller such as HDMI. For this reason the DC node itself is not enabled/disabled in DT; the DC itself is considered a shared resource, not the final (board-specific) display output. The node should instantiate a display output driver only if the rgb subnode is enabled. Other output drivers are free to use the DC if they are enabled and their DT node references the DC's DT node. Adapt the Tegra display drivers' bind() routine to only bind to the DC's DT node if the RGB subnode is enabled. Now that the display driver does the right thing, remove the workaround for this issue from Seaboard's DT file. Cc: Thierry Reding <treding@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com> Acked-by:
Thierry Reding <treding@nvidia.com> Reviewed-by:
Simon Glass <sjg@chromium.org>
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Stefan Agner authored
According to the product website, the full names are i.MX 7Solo and i.MX 7Dual, whereas the short form is i.MX7S and i.MX7D. Be consistent and print the short form for both supported i.MX 7 SoCs. Signed-off-by:
Stefan Agner <stefan@agner.ch> Reviewed-by:
Fabio Estevam <fabio.estevam@nxp.com>
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Stefan Agner authored
The clock parent of the AHB root clock when using mux option 1 is the SYS PLL 270MHz clock. This is specified in Table 5-11 Clock Root Table of the i.MX 7Dual Applications Processor Reference Manual. While it could be a documentation error, the 270MHz parent is also mentioned in the boot ROM configuration in Table 6-28: The clock is by default at 135MHz due to a POST_PODF value of 1 (=> divider of 2). Signed-off-by:
Stefan Agner <stefan@agner.ch>
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Stefan Agner authored
Several UART input selects are missing. The fourth input select for UART2_TX_DATA_ALT0 is actually also missing in the documentation. (at least in Rev. B of the i.MX 7Dual Reference Manual). However, when looking at the tables of other input selects, it is very natural that there must be an input select for the UART2_TX_DATA_ALT0 pad. The Colibri iMX7 also uses that pad for UART2 RX (in DTE mode), and it was required to set that particular input select register to get a working UART2.
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Eric Nelson authored
This patch adds the IOMUX setting for using SD1_DAT5 as GPIO5:9. Signed-off-by:
Eric Nelson <eric@nelint.com> Reviewed-by:
Peng Fan <van.freenix@gmail.com>
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- May 12, 2016
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Andre Przywara authored
Commit bfb33f0b ("sunxi: mctl_mem_matches: Add missing memory barrier") broke compilation for the Pine64, as dram_helper.c now includes <asm/armv7.h>, which does not compile on arm64. Fix this by moving all barrier instructions into a separate header file, which can easily be shared between arm and arm64. Also extend the inline assembly to take the "sy" argument, which is optional for ARMv7, but mandatory for v8. This fixes compilation for 64-bit sunxi boards (Pine64). Acked-by:
Ian Campbell <ijc@hellion.org.uk> Signed-off-by:
Andre Przywara <andre.przywara@arm.com>
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