- Oct 25, 2012
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Stephen Warren authored
cur_part_info.{name,type} are strings. So, we don't need to memset() the entire thing, just put the NULL-termination in the first byte. Add missing initialization of the bootable and uuid fields. None of these fields are actually used by fat.c. However, since it stores the entire disk_partition_t, we should make sure that all fields are valid. Signed-off-by:Stephen Warren <swarren@nvidia.com> Reviewed-by:
Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
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Stephen Warren authored
A future patch will implement the more standard filesystem API fat_set_blk_dev(). This API has no way to know which partition number the partition represents. Equally, future DM rework will make the concept of partition number harder to pass around. So, simply remove cur_part_nr from fat.c; its only use is in a diagnostic printf, and the context where it's printed should make it obvious which partition is referred to anyway (since the partition ID would come from the user command-line that caused it). Signed-off-by:
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Kim Phillips authored
serial_ns16550.c:222:1: warning: symbol 'eserial1_init' was not declared. Should it be static? serial_ns16550.c:222:1: warning: symbol 'eserial1_setbrg' was not declared. Should it be static? serial_ns16550.c:222:1: warning: symbol 'eserial1_getc' was not declared. Should it be static? serial_ns16550.c:222:1: warning: symbol 'eserial1_tstc' was not declared. Should it be static? serial_ns16550.c:222:1: warning: symbol 'eserial1_putc' was not declared. Should it be static? serial_ns16550.c:222:1: warning: symbol 'eserial1_puts' was not declared. Should it be static? serial_ns16550.c:225:1: warning: symbol 'eserial2_init' was not declared. Should it be static? serial_ns16550.c:225:1: warning: symbol 'eserial2_setbrg' was not declared. Should it be static? serial_ns16550.c:225:1: warning: symbol 'eserial2_getc' was not declared. Should it be static? serial_ns16550.c:225:1: warning: symbol 'eserial2_tstc' was not declared. Should it be static? serial_ns16550.c:225:1: warning: symbol 'eserial2_putc' was not declared. Should it be static? serial_ns16550.c:225:1: warning: symbol 'eserial2_puts' was not declared. Should it be static? serial_ns16550.c:228:1: warning: symbol 'eserial3_init' was not declared. Should it be static? serial_ns16550.c:228:1: warning: symbol 'eserial3_setbrg' was not declared. Should it be static? serial_ns16550.c:228:1: warning: symbol 'eserial3_getc' was not declared. Should it be static? serial_ns16550.c:228:1: warning: symbol 'eserial3_tstc' was not declared. Should it be static? serial_ns16550.c:228:1: warning: symbol 'eserial3_putc' was not declared. Should it be static? serial_ns16550.c:228:1: warning: symbol 'eserial3_puts' was not declared. Should it be static? serial_ns16550.c:231:1: warning: symbol 'eserial4_init' was not declared. Should it be static? serial_ns16550.c:231:1: warning: symbol 'eserial4_setbrg' was not declared. Should it be static? serial_ns16550.c:231:1: warning: symbol 'eserial4_getc' was not declared. Should it be static? serial_ns16550.c:231:1: warning: symbol 'eserial4_tstc' was not declared. Should it be static? serial_ns16550.c:231:1: warning: symbol 'eserial4_putc' was not declared. Should it be static? serial_ns16550.c:231:1: warning: symbol 'eserial4_puts' was not declared. Should it be static? Signed-off-by:Kim Phillips <kim.phillips@freescale.com>
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Kim Phillips authored
fsl_i2c.c:217:14: warning: symbol 'get_i2c_clock' was not declared. Should it be static? Signed-off-by:
Heiko Schocher <hs@denx.de>
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- Oct 24, 2012
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Alison Wang authored
Add Freescale MCF54418TWR ColdFire development board support. Signed-off-by:
TsiChung Liew <tsicliew@gmail.com> Signed-off-by:
Jason Jin <Jason.jin@freescale.com> Signed-off-by:
Alison Wang <b18965@freescale.com>
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Alison Wang authored
Add MCF5441x CPU support. The MCF5441x devices are a family of highly-integrated 32-bit microprocessors based on the Version 4m ColdFire microarchitecture, comprising of the V4 integer core, memory management unit(MMU) and enchanced multiply-accumulate unit(EMAC). Signed-off-by:
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Alison Wang authored
Fix the following build warnings in cpu_init.c: cpu_init.c: In function 'cpu_init_f': cpu_init.c:47:9: warning: unused variable 'pll' cpu_init.c:46:10: warning: unused variable 'fbcs' cpu_init.c:44:10: warning: unused variable 'scm1' Signed-off-by:
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- Oct 23, 2012
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Gerlando Falauto authored
Add support for the new kmvect1 board powered by the mpc8309 processor. As this board is very similar to the existing suvd3, instead of adding a new config header file, just add a new config option to suvd3.h Signed-off-by:
Gerlando Falauto <gerlando.falauto@keymile.com> Signed-off-by:
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Gerlando Falauto authored
Add support for Keymile boards based on mpc8309 (it would be only kmvect1 for now) Signed-off-by:
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Gerlando Falauto authored
This processor, though very similar to other members of the PowerQUICC II Pro family (namely 8308, 8360 and 832x), provides yet another feature set than any supported sibling. Signed-off-by:
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Gerlando Falauto authored
Introduce a new configuration token CONFIG_MPC830x to be shared among mpc8308 and mpc8309. Define it for existing 8308 boards, and refactor existing common code so to make future introduction of 8309 simpler. Signed-off-by:
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Gerlando Falauto authored
simplify #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) for qe variables with #if defined(CONFIG_QE) Signed-off-by:
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Gerlando Falauto authored
Signed-off-by:
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git://git.denx.de/u-boot-fdtTom Rini authored
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Gerald Van Baren authored
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- Oct 22, 2012
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git://www.denx.de/git/u-boot-mmcTom Rini authored
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Andy Fleming authored
The timeout_save variable was only used by the DDR111_134 erratum code. It was being set, but never used. Newer compilers will actually complain about this. Signed-off-by:Andy Fleming <afleming@freescale.com>
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Liu Gang authored
Currently, the SRIO and PCIE boot master module will be compiled into the u-boot image if the macro "CONFIG_FSL_CORENET" has been defined. And this macro has been included by all the corenet architecture platform boards. But in fact, it's uncertain whether all corenet platform boards support this feature. So it may be better to get rid of the macro "CONFIG_FSL_CORENET", and add a special macro for every board which can support the feature. This special macro will be defined in the header file "arch/powerpc/include/asm/config_mpc85xx.h". It will decide if the SRIO and PCIE boot master module should be compiled into the board u-boot image. Signed-off-by:
Liu Gang <Gang.Liu@freescale.com> Signed-off-by:
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Mingkai Hu authored
LAN8720 PHY is used on Freescale C2X0QDS board. Signed-off-by:
Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by:
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Shaohui Xie authored
Current espi controller driver assumes the command length of write command is not equal to '1', it was made based on SPANSION SPI flash, but some SPI flash driver such as SST does use write command length as '1', so write command on SST SPI flash will not work. And the length check for write command is not necessary for SPANSION, though it's harmless for SPANSION, it will stop write operation on flashes like SST, so we remove the check. Signed-off-by:
Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by:
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Shaohui Xie authored
TBI PHY address (TBIPA) register is set in general frame manager phy init funciton dtsec_init_phy() in drivers/net/fm/eth.c, and it is supposed to set TBIPA on FM1@DTSEC1 in case of FM1@DTSEC1 isn't used directly, which provides MDIO for other ports. So following code is wrong in case of FM2, which has a different mac base. struct dtsec *regs = (struct dtsec *)fm_eth->mac->base; /* Assign a Physical address to the TBI */ out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE); Signed-off-by:
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Haiying Wang authored
Starting from QMan3.0, the QMan clock cycle needs be exposed so that the kernel driver can use it to calculate the shaper prescaler and rate. Signed-off-by:
Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by:
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Haiying Wang authored
Because QMan3.0 and BMan2.1 used ip_cfg in ip_rev_2 register to differ the total portal number, buffer pool number etc, we can use this info to limit those resources in kernel driver. Signed-off-by:
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York Sun authored
The T4240QDS is a high-performance computing evaluation, development and test platform supporting the T4240 QorIQ Power Architecture™ processor. SERDES Connections 32 lanes grouped into four 8-lane banks Two “front side” banks dedicated to Ethernet Two “back side” banks dedicated to other protocols DDR Controllers Three independant 64-bit DDR3 controllers Supports rates up to 2133 MHz data-rate Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller QIXIS System Logic FPGA Each DDR controller has two DIMM slots. The first slot of each controller has up to 4 chip selects to support single-, dual- and quad-rank DIMMs. The second slot has only 2 chip selects to support single- and dual-rank DIMMs. At any given time, up to total 4 chip selects can be used. Detail information can be found in doc/README.t4qds Signed-off-by:
York Sun <yorksun@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org> Signed-off-by:
Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by:
Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by:
Roy Zang <tie-fei.zang@freescale.com> Signed-off-by:
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York Sun authored
New corenet platforms with chassis2 have separated DDR clock inputs. Use CONFIG_DDR_CLK_FREQ for DDR clock. This patch also cleans up the logic of detecting and displaying synchronous vs asynchronous mode. Signed-off-by:
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York Sun authored
Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined. 'M' bit is set for DDR TLB to maintain cache coherence. See details in doc/README.mpc85xx-spin-table. Signed-off-by:
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York Sun authored
R6 was in ePAPR draft version but was dropped in official spec. Removing it to comply. Signed-off-by:
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York Sun authored
Since empty DIMM slot is allowed on other than the first slot, remove the error message if SPD is not found in this case. Signed-off-by:
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York Sun authored
Based on populated DIMMs, automatically select from cs0_cs1_cs2_cs3 or cs0_cs1 interleaving, or non-interleaving if not available. Fix the message of interleaving disabled if controller interleaving is enabled but DIMMs don't support it. Signed-off-by:
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York Sun authored
After DDR controller is enabled, it performs a calibration for the transmit data vs DQS paths. During this calibration, the DDR controller may make an inaccurate calculation, resulting in a non-optimal tap point. Signed-off-by:
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York Sun authored
Boot space translation utilizes the pre-translation address to select the DDR controller target. However, the post-translation address will be presented to the selected DDR controller. It is possible that the pre- translation address selects one DDR controller but the post-translation address exists in a different DDR controller when using certain DDR controller interleaving modes. The device may fail to boot under these circumstances. Note that a DDR MSE error will not be detected since DDR controller bounds registers are programmed to be the same when configured for DDR controller interleaving. Signed-off-by:
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York Sun authored
When ECC is enabled, DDR controller needs to initialize the data and ecc. The wait time can be calcuated with total memory size, bus width, bus speed and interleaving mode. If it went wrong, it is bettert to timeout than waiting for D_INIT to clear, where it probably hangs. Signed-off-by:
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York Sun authored
Fix handling quad-rank DIMMs in a system with two DIMM slots and first slot supports both dual-rank DIMM and quad-rank DIMM. For systems with quad-rank DIMM and double dual-rank DIMMs, cs_config registers need to be enabled to maintain proper ODT operation. The inactive CS should have bnds registers cleared. Fix the turnaround timing for systems with all chip-selects enabled. This wasn't an issue before because DDR was running lower than 1600MT/s with this interleaving mode. Fix DDR address calculation. It wasn't an issue until we have multiple controllers with each more than 4GB and interleaving is disabled. It also fixes the message of DDR: 2 GiB (DDR3, 64-bit, CL=0.5, ECC off) when debugging DDR and first DDR controller is disabled. With the fix, the first enabled controller information will be displayed. Signed-off-by:
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York Sun authored
DDRC ver 4.7 adds DDR_SLOW bit in sdram_cfg_2 register. This bit needs to be set for speed lower than 1250MT/s. CDR1 and CDR2 are control driver registers. ODT termination valueis for IOs are defined. Starting from DDRC 4.7, the decoding of ODT for IOs is 000 -> Termsel off 001 -> 120 Ohm 010 -> 180 Ohm 011 -> 75 Ohm 100 -> 110 Ohm 101 -> 60 Ohm 110 -> 70 Ohm 111 -> 47 Ohm Add two write leveling registers. Each QDS now has its own write leveling start value. In case of zero value, the value of QDS0 will be used. These values are board-specific and are set in board files. Extend DDR register timing_cfg_1 to have 4 bits for each field. DDR control driver registers and write leveling registers are added to interactive debugging for easy access. Signed-off-by:
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Roy Zang authored
The multirate ethernet media access controller (mEMAC) interfaces to 10Gbps and below Ethernet/IEEE 802.3 networks via either RGMII/RMII interfaces or XAUI/XFI/SGMII/QSGMII using the high-speed SerDes interface. Signed-off-by:
Sandeep Singh <Sandeep@freescale.com> Signed-off-by:
Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by:
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York Sun authored
Add support for Freescale B4860 and variant SoCs. Features of B4860 are (incomplete list): Six fully-programmable StarCore SC3900 FVP subsystems, divided into three clusters-each core runs up to 1.2 GHz, with an architecture highly optimized for wireless base station applications Four dual-thread e6500 Power Architecture processors organized in one cluster-each core runs up to 1.8 GHz Two DDR3/3L controllers for high-speed, industry-standard memory interface each runs at up to 1866.67 MHz MAPLE-B3 hardware acceleration-for forward error correction schemes including Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate acceleration CoreNet fabric that fully supports coherency using MESI protocol between the e6500 cores, SC3900 FVP cores, memories and external interfaces. CoreNet fabric interconnect runs at 667 MHz and supports coherent and non-coherent out of order transactions with prioritization and bandwidth allocation amongst CoreNet endpoints. Data Path Acceleration Architecture, which includes the following: Frame Manager (FMan), which supports in-line packet parsing and general classification to enable policing and QoS-based packet distribution Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading of queue management, task management, load distribution, flow ordering, buffer management, and allocation tasks from the cores Security engine (SEC 5.3)-crypto-acceleration for protocols such as IPsec, SSL, and 802.16 RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and outbound). Supports types 5, 6 (outbound only) Large internal cache memory with snooping and stashing capabilities for bandwidth saving and high utilization of processor elements. The 9856-Kbyte internal memory space includes the following: 32 Kbyte L1 ICache per e6500/SC3900 core 32 Kbyte L1 DCache per e6500/SC3900 core 2048 Kbyte unified L2 cache for each SC3900 FVP cluster 2048 Kbyte unified L2 cache for the e6500 cluster Two 512 Kbyte shared L3 CoreNet platform caches (CPC) Sixteen 10-GHz SerDes lanes serving: Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total of up to 8 lanes Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue- less antenna connection Two 10-Gbit Ethernet controllers (10GEC) Six 1G/2.5-Gbit Ethernet controllers for network communications PCI Express controller Debug (Aurora) Two OCeaN DMAs Various system peripherals 182 32-bit timers Signed-off-by: -
York Sun authored
Add support for Freescale T4240 SoC. Feature of T4240 are (incomplete list): 12 dual-threaded e6500 cores built on Power Architecture® technology Arranged as clusters of four cores sharing a 2 MB L2 cache. Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture v2.06-compliant) Three levels of instruction: user, supervisor, and hypervisor 1.5 MB CoreNet Platform Cache (CPC) Hierarchical interconnect fabric CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet end-points 1.6 Tbps coherent read bandwidth Queue Manager (QMan) fabric supporting packet-level queue management and quality of service scheduling Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Memory prefetch engine (PMan) Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: Packet parsing, classification, and distribution (Frame Manager 1.1) Queue management for scheduling, packet sequencing, and congestion management (Queue Manager 1.1) Hardware buffer management for buffer allocation and de-allocation (BMan 1.1) Cryptography acceleration (SEC 5.0) at up to 40 Gbps RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0) 32 SerDes lanes at up to 10.3125 GHz Ethernet interfaces Up to four 10 Gbps Ethernet MACs Up to sixteen 1 Gbps Ethernet MACs Maximum configuration of 4 x 10 GE + 8 x 1 GE High-speed peripheral interfaces Four PCI Express 2.0/3.0 controllers Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with Type 11 messaging and Type 9 data streaming support Interlaken look-aside interface for serial TCAM connection Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Four I2C controllers Four 2-pin or two 4-pin UARTs Integrated Flash controller supporting NAND and NOR flash Two eight-channel DMA engines Support for hardware virtualization and partitioning enforcement QorIQ Platform's Trust Architecture 1.1 Signed-off-by: -
Andy Fleming authored
The T4 has added devices to previous corenet implementations: * SEC has 3 more DECO units * New PMAN device * New DCE device This doesn't add full support for the new devices. Just some preliminary support. Move PMAN LIODN to upper half of register Despite having only one LIODN, the PMAN LIODN is stored in the upper half of the register. Re-use the 2-LIODN code and just set the LIODN as if the second one is 0. This results in the actual LIODN being written to the upper half of the register. Signed-off-by: -
Shaveta Leekha authored
Add code for configuring VSC3316/3308 crosspoint switches Add README to understand the APIs - VSC 3316/3308 is a low-power, low-cost asynchronous crosspoint switch capable of data rates upto 11.5Gbps. VSC3316 has 16 input and 16 output ports whereas VSC3308 has 8 input and 8 output ports. Programming of these devices are performed by two-wire or four-wire serial interface. Signed-off-by:Shaveta Leekha <shaveta@freescale.com> Signed-off-by:
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