Commit ffd06e02 authored 12 years ago by York Sun Committed by Andy Fleming 12 years ago

powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1


Move spin table to cached memory to comply with ePAPR v1.1.
Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.

'M' bit is set for DDR TLB to maintain cache coherence.

See details in doc/README.mpc85xx-spin-table.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

parent 3f0997b3

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