add support for imx6dl based aristainetos2 board

U-Boot 2015.04-rc5-00066-g60f6ed4 (Apr 10 2015 - 08:46:27)

CPU:   Freescale i.MX6DL rev1.1 at 792 MHz
Reset cause: WDOG
Board: aristaitenos2
       Watchdog enabled
I2C:   ready
DRAM:  1 GiB
NAND:  1024 MiB
MMC:   FSL_SDHC: 0
SF: Detected N25Q128A with page size 256 Bytes, erase size 64 KiB, total 16 MiB
Display: lg4573 (480x800)
In:    serial
Out:   serial
Err:   serial
Net:   FEC [PRIME]
Hit any key to stop autoboot:  0
=>

Signed-off-by: Heiko Schocher <hs@denx.de>

rework and unify i2c address names for different SoCs, which
use the mxc_i2c driver.

Signed-off-by: Heiko Schocher <hs@denx.de>

add I2C4 modul for MX6DL based boards.

Signed-off-by: Heiko Schocher <hs@denx.de>

We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee
that socs' cache line size is 32 bytes.
If on chips whose cache line size is 64 bytes, error occurs:
"
NAND:  ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0
ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0
ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0
"
Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to
CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>

The break after return is unreachable code, remove it.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>

pwm_id_to_reg() can return NULL, so add NULL testing to prevent NULL pointer
dereference.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>

Falcon mode entails the SPL booting the OS directly instead of U-Boot.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

Currently we need to build one U-boot image for each of the wandboard
variants: quad, dual-lite and solo.

By switching to SPL we can support all these variants with a single binary,
which is very convenient.

Based on the work from Richard Hu.

Tested kernel booting on the three boards.

Signed-off-by: Richard Hu <hakahu@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Vagrant Cascadian <vagrant@aikidev.net>
Reviewed-by: Stefano Babic <sbabic@denx.de>

Replace the hard-coded values for min/max/passive with values derived from
the CPU temperature grade.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

When CONFIG_IMX6_THERMAL is defined print the CPU temperature grade info
along with the current temperature.

Before:
 CPU:   Temperature 42 C

After:
 CPU:   Automotive temperature grade (-40C to 125C) at 42C
 CPU:   Industrial temperature grade (-40C to 105C) at 42C
 CPU:   Extended Commercial temperature grade (-20C to 105C) at 42C

Cc: Stefan Roese <sr@denx.de>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Jon Nettleton <jon.nettleton@gmail.com>
Cc: Jason Liu <r64343@freescale.com>
Cc: Ye Li <b37916@freescale.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Cc: Peng Fan <b51431@freescale.com>
Tested-by: Nikolay Dimitrov <picmaster@mail.bg>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>

The MX6 has a temperature grade defined by OCOTP_MEM0[7:6] which is at 0x480
in the Fusemap Description Table in the reference manual. Return this value
as well as min/max temperature based on the value.

Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the
their Fusemap Description Table however Freescale has confirmed that these
eFUSE bits match the description within the IMX6DQRM and that they will
be added to the next revision of the respective reference manuals.

This has been tested with IMX6 Automative and Industrial parts.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

Display the max CPU frequency as well as the current running CPU frequency
if the max CPU frequency is available and differs from the current CPU
frequency.

Before:
CPU:   Freescale i.MX6Q rev1.2 at 792 MHz

After - using an 800MHz IMX6DL (running at its max)
CPU:   Freescale i.MX6DL rev1.1 at 792 MHz

After - using a 1GHz IMX6Q (not running at its max):
CPU:   Freescale i.MX6Q rev1.2 996 MHz (running at 792 MHz)

Cc: Stefan Roese <sr@denx.de>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Jon Nettleton <jon.nettleton@gmail.com>
Cc: Jason Liu <r64343@freescale.com>
Cc: Ye Li <b37916@freescale.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Cc: Peng Fan <b51431@freescale.com>
Tested-by: Nikolay Dimitrov <picmaster@mail.bg>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>

The IMX6 has four different speed grades determined by eFUSE SPEED_GRADING
indicated by OCOTP_CFG3[17:16] which is at 0x440 in the Fusemap Description
Table. Return this frequency so that it can be used elsewhere.

Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the
their Fusemap Description Table however Freescale has confirmed that these
eFUSE bits match the description within the IMX6DQRM and that they will
be added to the next revision of the respective reference manuals.

These have been tested with IMX6 Quad/Solo/Dual-light 800Mhz and 1GHz grades.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

Commit fa8b7d66f49f0c7bd41467fe78f6488d8af6976a introduced fast-exit support
to the MMDC however enabling it on the DDR3 got missed. Make sure we enable
it on the DDR3 as well.

Gateworks uses Micron memory as well as Winbond in MX6. We have found in
testing that we need to enable fast-exit for Winbond stability. Gateworks
boards are currently the only boards using the MX6 SPL and enabling
fast-exit mode.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

Fix below warning
arch/arm/imx-common/cpu.c:29:14: warning: ‘get_reset_cause’ defined but
not used
 static char *get_reset_cause(void)

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>

Change PUZE_100_SW1ABCONF to PFUZE100_SW1ABCONF

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>

Enable IOMUX_CONFIG_SION for all I2C pin mux settings, otherwise
we will get erros when doing i2c operations.
error log like the following:
"
wait_for_sr_state: failed sr=81 cr=a0 state=2020
i2c_init_transfer: failed for chip 0xb retry=1
"

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>

Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg>

Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg>

Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg>

The 'mx6-microsom' directory was only used for the previous mx6solo
hummingboard support, which has been removed in favour of the SPL
version.

Remove the remaining piece of the old mx6solo hummingboard support.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>

We need to do any PMIC setup in the SPL if we are to bypass U-Boot for
falcon mode.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

Use the SZ_1M and SZ_1K macros from linuz/sizes.h for improved readability

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

Switch to MMC RAW support for SPL. We will place the uboot.img at 69KB.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

The readenv() implementation of env_nand uses the mtd layer which is
unnecessary overhead in SPL when we already have a nand_spl_load_image()
function that doesn't need it. Using this instead eliminates the need
to provide a mtd_read for SPL env as well as reduces code (4KB savings in IMX6
SPL).

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Acked-by: Scott Wood <scottwood@freescale.com>

Certain features we desire require a larger stack than is available by using
iRAM (most notably for us, env_mmc). Relocate the stack to DRAM so that
we can use these features.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

If the SPL is to be used for Falcon mode then we need to make sure the SPL
disable the GSC boot watchdog.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

If the SPL is to be used for Falcon mode then we need to make sure it
configures basic GPIO (iomux, padconf, and default output levels).

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

Now that uart and i2c setup functions have been moved to common.c we can
use these and remove code duplication.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

Avoid requiring board-model and probe pmic by its i2c address.
This is in preparation for being able to call pmic_setup() from SPL
and not need board type.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

Move the code that disables the GSC boot watchdog into gsc.c

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

Move shared functions used by both SPL and U-Boot to common.c:
 - setup_iomux_uart() and uart pad config
 - gpio pad config

In the process also moved the following to common.c in preparation for
calling it from the SPL:
 - split i2c setup into a shared function
 - move pmic init to setup_pmic() function to call directly from
   power_init_board()
 - split gpio setup into early (iomux and default pin config)
   and late (output configuration based on env)

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

PCI enumeration occurs early, before we fully configure our GPIO's. Make
sure we steer the MSATA/PCI mux to PCI in board_init to ensure PCI is
selected before enumeration.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

The re-assignment of pcie_rst gpio for GW522x needs to occur earlier, before
the PCI subsystem calls the toggle funciton.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

mxc_serial supports DM so lets use it.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

Prior to using a gpio a call to gpio_request() should be called to register
it with the gpio subsystem.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

Enable U-Boot Driver Model (DM).

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

Signed-off-by: Tim Harvey <tharvey@gateworks.com>