(Dot outside sections problem).

This fix is in the spirit of 807d5d73.

Signed-off-by: Jon Loeliger <jdl@freescale.com>

Prevent false interrupt from hanging Linux as MSR[EE] is set
to enable interrupts by changing the PIC out of the default
pass through mode into mixed mode.

Signed-off-by: Haiying Wang <haiying.wang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>

Also fixes some commmand for 8641 HPCN ramboot case.

Signed-off-by: Jason Jin <jason.jin@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>

Without this patch, I am unable to get to the prompt on rev 2 silicon.
Only set ddrioovcr for rev1.

Signed-off-by: Ed <Swarthout&lt;ed.swarthout@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>

                 for the SIUMCR and BCR Register.
                 Fix the calculation for the EEprom Size

Signed-off-by: Heiko Schocher <hs@denx.de>

Signed-off-by: Wolfgang Denk <wd@denx.de>

Define CONFIG_PROG_SDRAM_TLB so that the TLB entries for the
DDR memory are dynamically programmed matching the total size
of the equipped memory (DIMM modules).

Signed-off-by: Stefan Roese <sr@denx.de>

        boards in terms of unification.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>

(SC3 and Jupiter used to use 'addcon' instead).

Signed-off-by: Wolfgang Denk <wd@denx.de>

        added Hush Shell,
              CONFIG_CMDLINE_EDITING,
              CFG_ENV_ADDR_REDUND activated

Signed-off-by: Heiko Schocher <hs@denx.de>

Signed-off-by: Stefan Roese <sr@denx.de>

Signed-off-by: John Otken john@softadvances.com <john@softadvances.com>

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>

The AMCC Luan now uses the common 440SP(e) DDR SPD code for DDR
inititializition. This includes DDR auto calibration and support
for different DIMM modules, instead of the fixed setup used in
the earlier version.

This patch also enables the cache in FLASH for the startup
phase of U-Boot (while running from FLASH). After relocating to
SDRAM the cache is disabled again. This will speed up the boot
process, especially the SDRAM setup, since there are some loops
for memory testing (auto calibration).

Signed-off-by: Stefan Roese <sr@denx.de>

The AMCC Yucca now uses the common 440SP(e) DDR SPD code for DDR
inititializition. This includes DDR auto calibration and support
for different DIMM modules, instead of the fixed setup used in
the earlier version.

Signed-off-by: Stefan Roese <sr@denx.de>

Signed-off-by: Stefan Roese <sr@denx.de>

Signed-off-by: Stefan Roese <sr@denx.de>

Define CONFIG_PROG_SDRAM_TLB so that the TLB entries for the
DDR memory are dynamically programmed matching the total size
of the equipped memory (DIMM modules).

Signed-off-by: Stefan Roese <sr@denx.de>

This patch fixes a problem that occurs when 2 DIMM's are
used. This problem was first spotted and fixed by Gerald Jackson
<gerald.jackson@reaonixsecurity.com> but this patch fixes the
problem in a little more clever way.

This patch also adds the nice functionality to dynamically
create the TLB entries for the SDRAM (tlb.c). So we should
never run into such problems with wrong (too short) TLB
initialization again on these platforms.

As this feature is new to the "old" 44x SPD DDR driver, it
has to be enabled via the CONFIG_PROG_SDRAM_TLB define.

Signed-off-by: Stefan Roese <sr@denx.de>

Patch by Mike Frysinger, Mar 05 2007

As provided by the AMCC applications team, this patch optimizes the
DDR2 setup for 166MHz bus speed. The values provided are also save
to use on a "normal" 133MHz PLB bus system. Only the refresh counter
setup has to be adjusted as done in this patch.

For this the NAND booting version had to include the "speed.c" file
from the cpu/ppc4xx directory. With this addition the NAND SPL image
will just fit into the 4kbytes of program space. gcc version 4.x as
provided with ELDK 4.x is needed to generate this optimized code.

Signed-off-by: Stefan Roese <sr@denx.de>

(cherry picked from c5bf13b02284c3204a723566a9bab700e5059659 commit)