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Jack Humbert
reform-boundary-uboot
Commits
46270c28
Commit
46270c28
authored
18 years ago
by
Wolfgang Denk
Committed by
Wolfgang Denk
18 years ago
Browse files
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Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xx
parents
39218433
fa1aef15
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Changes
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3 changed files
board/amcc/ocotea/init.S
+19
-63
19 additions, 63 deletions
board/amcc/ocotea/init.S
cpu/ppc4xx/44x_spd_ddr.c
+27
-4
27 additions, 4 deletions
cpu/ppc4xx/44x_spd_ddr.c
include/configs/ocotea.h
+2
-1
2 additions, 1 deletion
include/configs/ocotea.h
with
48 additions
and
68 deletions
board/amcc/ocotea/init.S
+
19
−
63
View file @
46270c28
...
...
@@ -22,55 +22,7 @@
#include <ppc_asm.tmpl>
#include <config.h>
/*
General
*/
#define TLB_VALID 0x00000200
#define _256M 0x10000000
/*
Supported
page
sizes
*/
#define SZ_1K 0x00000000
#define SZ_4K 0x00000010
#define SZ_16K 0x00000020
#define SZ_64K 0x00000030
#define SZ_256K 0x00000040
#define SZ_1M 0x00000050
#define SZ_8M 0x00000060
#define SZ_16M 0x00000070
#define SZ_256M 0x00000090
/*
Storage
attributes
*/
#define SA_W 0x00000800 /* Write-through */
#define SA_I 0x00000400 /* Caching inhibited */
#define SA_M 0x00000200 /* Memory coherence */
#define SA_G 0x00000100 /* Guarded */
#define SA_E 0x00000080 /* Endian */
/*
Access
control
*/
#define AC_X 0x00000024 /* Execute */
#define AC_W 0x00000012 /* Write */
#define AC_R 0x00000009 /* Read */
/*
Some
handy
macros
*/
#define EPN(e) ((e) & 0xfffffc00)
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
#define TLB2(a) ( (a)&0x00000fbf )
#define tlbtab_start\
mflr
r1
;\
bl
0
f
;
#define tlbtab_end\
.
long
0
,
0
,
0
; \
0
:
mflr
r0
; \
mtlr
r1
; \
blr
;
#define tlbentry(epn,sz,rpn,erpn,attr)\
.
long
TLB0
(
epn
,
sz
),
TLB1
(
rpn
,
erpn
),
TLB2
(
attr
)
#include <asm-ppc/mmu.h>
/**************************************************************************
*
TLB
TABLE
...
...
@@ -83,19 +35,23 @@
*
*************************************************************************/
.
section
.
bootpg
,
"ax"
.
globl
tlbtab
.
section
.
bootpg
,
"ax"
.
globl
tlbtab
tlbtab
:
tlbtab_start
tlbentry
(
0xf0000000
,
SZ_256M
,
0xf0000000
,
1
,
AC_R|AC_W|AC_X|SA_G|SA_I
)
tlbentry
(
CFG_PERIPHERAL_BASE
,
SZ_256M
,
0x40000000
,
1
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_ISRAM_BASE
,
SZ_4K
,
0x80000000
,
0
,
AC_R|AC_W|AC_X
)
tlbentry
(
CFG_ISRAM_BASE
+
0x1000
,
SZ_4K
,
0x80001000
,
0
,
AC_R|AC_W|AC_X
)
tlbentry
(
CFG_SDRAM_BASE
,
SZ_256M
,
0x00000000
,
0
,
AC_R|AC_W|AC_X|SA_G|SA_I
)
tlbentry
(
CFG_SDRAM_BASE
+
0x10000000
,
SZ_256M
,
0x10000000
,
0
,
AC_R|AC_W|AC_X|SA_G|SA_I
)
tlbentry
(
CFG_SDRAM_BASE
+
0x20000000
,
SZ_256M
,
0x20000000
,
0
,
AC_R|AC_W|AC_X|SA_G|SA_I
)
tlbentry
(
CFG_SDRAM_BASE
+
0x30000000
,
SZ_256M
,
0x30000000
,
0
,
AC_R|AC_W|AC_X|SA_G|SA_I
)
tlbentry
(
CFG_PCI_BASE
,
SZ_256M
,
0x00000000
,
2
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCI_MEMBASE
,
SZ_256M
,
0x00000000
,
3
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbtab_end
tlbtab_start
tlbentry
(0
xf0000000
,
SZ_256M
,
0xf0000000
,
1
,
AC_R|AC_W|AC_X|SA_G|SA_I
)
/
*
*
TLB
entries
for
SDRAM
are
not
needed
on
this
platform
.
*
They
are
dynamically
generated
in
the
SPD
DDR
(
2
)
detection
*
routine
.
*/
tlbentry
(
CFG_PERIPHERAL_BASE
,
SZ_256M
,
0x40000000
,
1
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_ISRAM_BASE
,
SZ_4K
,
0x80000000
,
0
,
AC_R|AC_W|AC_X
)
tlbentry
(
CFG_ISRAM_BASE
+
0x1000
,
SZ_4K
,
0x80001000
,
0
,
AC_R|AC_W|AC_X
)
tlbentry
(
CFG_PCI_BASE
,
SZ_256M
,
0x00000000
,
2
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCI_MEMBASE
,
SZ_256M
,
0x00000000
,
3
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbtab_end
This diff is collapsed.
Click to expand it.
cpu/ppc4xx/44x_spd_ddr.c
+
27
−
4
View file @
46270c28
...
...
@@ -46,6 +46,7 @@
#include
<asm/processor.h>
#include
<i2c.h>
#include
<ppc4xx.h>
#include
<asm/mmu.h>
#if defined(CONFIG_SPD_EEPROM) && \
(defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
...
...
@@ -229,6 +230,22 @@
#define TRUE 1
#define FALSE 0
/*
* This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
* region. Right now the cache should still be disabled in U-Boot because of the
* EMAC driver, that need it's buffer descriptor to be located in non cached
* memory.
*
* If at some time this restriction doesn't apply anymore, just define
* CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
* everything correctly.
*/
#ifdef CFG_ENABLE_SDRAM_CACHE
#define MY_TLB_WORD2_I_ENABLE 0
/* enable caching on SDRAM */
#else
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE
/* disable caching on SDRAM */
#endif
const
unsigned
long
test
[
NUMMEMTESTS
][
NUMMEMWORDS
]
=
{
{
0x00000000
,
0x00000000
,
0xFFFFFFFF
,
0xFFFFFFFF
,
0x00000000
,
0x00000000
,
0xFFFFFFFF
,
0xFFFFFFFF
},
...
...
@@ -259,6 +276,7 @@ typedef struct bank_param BANKPARMS;
#ifdef CFG_SIMULATE_SPD_EEPROM
extern
unsigned
char
cfg_simulate_spd_eeprom
[
128
];
#endif
void
program_tlb
(
u32
start
,
u32
size
,
u32
tlb_word2_i_value
);
unsigned
char
spd_read
(
uchar
chip
,
uint
addr
);
...
...
@@ -377,6 +395,11 @@ long int spd_sdram(void) {
total_size
=
program_bxcr
(
dimm_populated
,
iic0_dimm_addr
,
num_dimm_banks
);
#ifdef CONFIG_PROG_SDRAM_TLB
/* this define should eventually be removed */
/* and program tlb entries for this size (dynamic) */
program_tlb
(
0
,
total_size
,
MY_TLB_WORD2_I_ENABLE
);
#endif
/*
* program SDRAM Clock Timing Register (SDRAM0_CLKTR)
*/
...
...
@@ -1330,11 +1353,11 @@ unsigned long program_bxcr(unsigned long* dimm_populated,
*/
cr
|=
SDRAM_BXCR_SDBE
;
for
(
i
=
0
;
i
<
num_banks
;
i
++
)
{
bank_parms
[
ctrl_bank_num
[
dimm_num
]
+
i
].
bank_size_bytes
=
for
(
i
=
0
;
i
<
num_banks
;
i
++
)
{
bank_parms
[
ctrl_bank_num
[
dimm_num
]
+
i
+
dimm_num
].
bank_size_bytes
=
(
4
*
1024
*
1024
)
*
bank_size_id
;
bank_parms
[
ctrl_bank_num
[
dimm_num
]
+
i
].
cr
=
cr
;
}
bank_parms
[
ctrl_bank_num
[
dimm_num
]
+
i
+
dimm_num
].
cr
=
cr
;
}
}
}
...
...
This diff is collapsed.
Click to expand it.
include/configs/ocotea.h
+
2
−
1
View file @
46270c28
...
...
@@ -148,8 +148,9 @@
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
#define CONFIG_SPD_EEPROM 1
/* Use SPD EEPROM for setup
*/
#define CONFIG_SPD_EEPROM 1
/* Use SPD EEPROM for setup */
#define SPD_EEPROM_ADDRESS {0x53,0x52}
/* SPD i2c spd addresses */
#define CONFIG_PROG_SDRAM_TLB 1
/* setup SDRAM TLB's dynamically*/
/*-----------------------------------------------------------------------
* I2C
...
...
This diff is collapsed.
Click to expand it.
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