Include config.h earlier in the set of #includes
so as to avoid a incidental and duplicate definition
of CFG_CACHELINE_SIZE.

Signed-off-by: Jon Loeliger

Doing so prevents it from being individually set
and useful in other files.

Signed-off-by: Jon Loeliger <jdl@freescale.com>

Assumes the presence of the aliases node in the DTS to
locate the ethernet, pci and serial nodes for fixups.

Use consistent fdtaddr and fdtfile in environment variables.

Signed-off-by: Jon Loeliger <jdl@freescale.com>

This bug was detected on the LWMON5 target which has 2 Intel 16bit wide
flash chips connected to a 32bit wide port.

Signed-off-by: Stefan Roese <sr@denx.de>

Signed-off-by: Wolfgang Denk <wd@denx.de>

The bash builtin versions of the "test" (resp. "[") command allow
using "==" for string comparisons, but POSIX compatible implemen-
tations (like /usr/bin/test) insist on using "=" only. On such systems
you will see:

	$ /usr/bin/test a == a && echo OK
	/usr/bin/test: ==: binary operator expected

This patch fixes Makefiles and scripts to use POSIX style.

Signed-off-by: Wolfgang Denk <wd@denx.de>

Signed-off-by: Wolfgang Denk <wd@denx.de>

Conflicts:

	cpu/ppc4xx/fdt.c
	include/configs/kilauea.h
	include/configs/sequoia.h

Signed-off-by: Stefan Roese <sr@denx.de>

Signed-off-by: Stefan Roese <sr@denx.de>

This patch brings the PMC440 board configuration file.
Finally it enables the PMC440 board support.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>

This patch adds some BSP commands and FPGA booting support
for esd's PMC440 boards.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>

This patch adds the first files for the new esd PMC440 boards.
The next two patches will complete the PMC440 board support.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>

- add EEPROM write protection for esd PLU405 boards.
- initialize NAND GPIOs
- use correct io accessors
- cleanup

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>

This patch fixes esd's LCD dectection code to work correctly with
newer gcc versions.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>

- add EEPROM write protection
- initialize NAND GPIOs
- use correct io accessors
- slow down I2C clock to 100kHz
- enable ext. I2C bus
- cleanup

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>

In an attmemt to clean up the 4xx start.S file, I removed the enabling
of the internal 405EP PCI arbiter. This is needed for multiple other
405EP platforms, like most of the esd 405EP. Now the internal PCI
arbiter is enabled again per default as it has been before.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>

Use correct link to nand_ecc now located in drivers/mtd/nand/ for the
platforms mentioned above.

Signed-off-by: Stefan Roese <sr@denx.de>

This board never left prototyping state and it
became a millstone round my neck. So remove it.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>

These patches add support for the PPC440EPx-based "Korat" board to
U-Boot.  They are based primarily on support for the Sequoia board.

Signed-off-by: Larry Johnson <lrj@acm.org>

This patch supplies the configuration file for the Korat PPC440EPx-
processor board.

Signed-off-by: Larry Johnson <lrj@acm.org>

Signed-off-by: Larry Johnson <lrj@acm.org>

This patch adds SPD DDR2 support for the 440EPx ("Denali") SDRAM
controller.  It should also work on the 440GRx.  It is based on the DDR2
SPD code for the 440EP/440EPx, but makes no provision for DDR1 support.

This code has been tested on prototype Korat boards with three Kingston
DIMMS: 512 MiB ECC (one rank), 512 MiB non-ECC (one rank) and 1 GiB ECC
(two ranks).  The Korat board has a single DIMM socket, but support has
been provided (though not tested) for boards with two DIMM sockets.

Signed-off-by: Larry Johnson <lrj@acm.org>

This patch creates a non-board-specific file for performing the SDRAM
data-eye search.  It also adds ECC error checking to the test of valid
data on readback when ECC is enabled.

Signed-off-by: Larry Johnson <lrj@acm.org>

This patch adds the Denali SDRAM controller definitions to "ppc440.h".
It also fixes two typos in the definitions, so the board-specific
"sdram.h" files containing these definitions are also fixed to avoid
compiler warnings.

Signed-off-by: Larry Johnson <lrj@acm.org>

This patch adds a new switch: "CONFIG_PHY_DYNAMIC_ANEG".  When this symbol
is defined, the PHY will advertise it's capabilities for autonegotiation
based on the capabilities shown in the PHY's status registers, including
1000BASE-X.  When "CONFIG_PHY_DYNAMIC_ANEG" is not defined, the PHY will
advertise hard-coded capabilities, as before.

Signed-off-by: Larry Johnson <lrj@acm.org>

This driver is based on the driver for the LM75.

Signed-off-by: Larry Johnson <lrj@acm.org>

This driver is based on the driver for the M41T11.  In the intended
application, the RTC will be powered by a large capacitor, rather than a
battery.  The driver therefore checks to see whether the RTC has lost
power.  The chip's OUT bit is normally reset from its power-up state.  If
the OUT bit is read as set, or if the date and time are not valid, then the
RTC is assumed to have lost power, and its date and time are reset to
1900-01-01 00:00:00.

Support for adjusting the speed of the clock to improve accuracy is
provided through an environment variable.

Signed-off-by: Larry Johnson <lrj@acm.org>

Signed-off-by: Larry Johnson <lrj@acm.org>

Signed-off-by: Larry Johnson <lrj@acm.org>

Signed-off-by: Larry Johnson <lrj@acm.org>

Signed-off-by: Stefan Roese <sr@denx.de>

On Sequoia & LWMON5 the virtual address of the POST cache test is now
moved to a bigger address. This enables usage of more memory on those
boards.

Signed-off-by: Stefan Roese <sr@denx.de>

As repoted by Larry Johnson, running "diag run cache" caused a crash
in U-Boot. This problem was introduced by a patch that removed the
TLB entry for the cache test after the test has completed. Since this
TLB was only setup once, a 2nd attempt to run this cache test
failed with a crash. Now this TLB entry is created every time the
routine is called.

Signed-off-by: Stefan Roese <sr@denx.de>

Signed-off-by: Stefan Roese <sr@denx.de>

Signed-off-by: Stefan Roese <sr@denx.de>