- May 31, 2020
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- May 30, 2020
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minute authored
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- May 28, 2020
- May 21, 2020
- Dec 05, 2019
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Troy Kisky authored
Signed-off-by:
Troy Kisky <troy.kisky@boundarydevices.com>
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- Dec 04, 2019
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Troy Kisky authored
Signed-off-by:
Troy Kisky <troy.kisky@boundarydevices.com>
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Troy Kisky authored
Signed-off-by:
Troy Kisky <troy.kisky@boundarydevices.com>
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Troy Kisky authored
This reverts commit 308ca269. Signed-off-by:
Troy Kisky <troy.kisky@boundarydevices.com>
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- Nov 25, 2019
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Troy Kisky authored
nw2 seems to need this change. Data sheet says 104 ns. This is a little more. Signed-off-by:
Troy Kisky <troy.kisky@boundarydevices.com>
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- Nov 23, 2019
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Troy Kisky authored
Signed-off-by:
Troy Kisky <troy.kisky@boundarydevices.com>
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Troy Kisky authored
Signed-off-by:
Troy Kisky <troy.kisky@boundarydevices.com>
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Troy Kisky authored
Signed-off-by:
Troy Kisky <troy.kisky@boundarydevices.com>
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Troy Kisky authored
Signed-off-by:
Troy Kisky <troy.kisky@boundarydevices.com>
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Troy Kisky authored
This seems to fix the flicker issue on i.MX8MM Signed-off-by:
Troy Kisky <troy.kisky@boundarydevices.com>
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Troy Kisky authored
This seems to fix the flicker issue on i.MX8MM Signed-off-by:
Troy Kisky <troy.kisky@boundarydevices.com>
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- Nov 20, 2019
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Troy Kisky authored
Signed-off-by:
Troy Kisky <troy.kisky@boundarydevices.com>
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- Nov 19, 2019
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Troy Kisky authored
Signed-off-by:
Troy Kisky <troy.kisky@boundarydevices.com>
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Troy Kisky authored
Signed-off-by:
Troy Kisky <troy.kisky@boundarydevices.com>
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Troy Kisky authored
Signed-off-by:
Troy Kisky <troy.kisky@boundarydevices.com>
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Troy Kisky authored
Signed-off-by:
Troy Kisky <troy.kisky@boundarydevices.com>
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Troy Kisky authored
Signed-off-by:
Troy Kisky <troy.kisky@boundarydevices.com>
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Peng Fan authored
Support pinctrl/clk/sdhc, include ddr4 timing data. Log: U-Boot SPL 2019.10-rc3-00356-g497c500423-dirty (Sep 16 2019 - 10:54:58 +0800) Normal Boot Trying to boot from BOOTROM image offset 0x8000, pagesize 0x200, ivt offset 0x0 U-Boot 2019.10-rc3-00356-g497c500423-dirty (Sep 16 2019 - 10:54:58 +0800) CPU: Freescale i.MX8MNano rev1.0 at 24 MHz Reset cause: POR Model: NXP i.MX8MNano DDR4 EVK board DRAM: 2 GiB MMC: FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: No ethernet found. Hit any key to stop autoboot: 0 Signed-off-by:
Peng Fan <peng.fan@nxp.com>
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Troy Kisky authored
Signed-off-by:
Troy Kisky <troy.kisky@boundarydevices.com>
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Kever Yang authored
SPL/TPL also need use sysreset for some feature like panic callback. Signed-off-by:
Kever Yang <kever.yang@rock-chips.com>
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Troy Kisky authored
Signed-off-by:
Troy Kisky <troy.kisky@boundarydevices.com>
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Peng Fan authored
Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by:
Peng Fan <peng.fan@nxp.com> ddr: imx8m: Fix ddr4 driver build issue Since the parameter of dram_pll_init is changed, update to use new. Also remove non-existed header file. Signed-off-by:
Ye Li <ye.li@nxp.com> Signed-off-by:
Peng Fan <peng.fan@nxp.com>
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Peng Fan authored
Add dtsi for i.MX8MN Signed-off-by:
Peng Fan <peng.fan@nxp.com>
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Peng Fan authored
Make reset_cpu only visible when CONFIG_SYSRESET not defined or CONFIG_SPL_BUILD. Signed-off-by:
Peng Fan <peng.fan@nxp.com>
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Peng Fan authored
Add cfg file for i.MX8MN DDR4 Signed-off-by:
Peng Fan <peng.fan@nxp.com>
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